Abstract: Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog outputs. In one example, a system comprises a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns; and an output circuit to receive a respective neuron current from respective columns of the vector by matrix multiplication array and to generate a respective output voltage, the output circuit comprising a neuron scalar to generate a scaled current from the received respective neuron current, and a current-to-voltage converter to convert the scaled current into the respective output voltage.

Abstract: In one example, a method comprises programming a plurality of analog neural non-volatile memory cells in an array of analog neural non-volatile memory cells to store one of N different values, where Nis a number of different levels that can be stored in any of the analog neural non-volatile memory cells; measuring a current drawn by the plurality of analog neural non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of the analog neural non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold.

Abstract: Examples of programming circuits and methods are provided. In one example, an adjustable programming circuit comprises a first adjustable voltage divider; a second adjustable voltage divider; a first operational amplifier, wherein an output terminal of the first operational amplifier provides a first programming voltage; and a second operational amplifier, wherein the first input terminal of the second operational amplifier is coupled to the output terminal of the second operational amplifier and the first input terminal of the second operational amplifier is coupled to the second output terminal of the first adjustable voltage divider.

Abstract: Examples for ultra-precise tuning of a selected memory cell are disclosed. In one example, a method of programming a first memory cell in a neural memory to a target value is disclosed, the method comprising programming a second memory cell by applying programming voltages to terminals of the second memory cell; and determining if an output of the first memory cell has reached the target value.

Abstract: Numerous examples are disclosed of systems and methods for operating one or more arrays of resistive random access memory (RRAM) cells. In one example, a system comprises an array of resistive random access memory (RRAM) units arranged in rows and columns; and a sense amplifier for determining a differential value stored in a first RRAM unit and a second RRAM unit in the array, wherein the first RRAM unit comprises a first select transistor coupled to a first set of one or more RRAM cells and the second RRAM unit comprises a second select transistor coupled to a second set of one or more RRAM cells.

Abstract: Numerous examples are disclosed of systems and methods for operating one or more arrays of resistive random access memory (RRAM) cells. In one example, a read bias generator comprises a bias transistor, a feedback loop, a replica resistor, and a reference unit. Optionally, the read bias generator is coupled to an array of RRAM units.

Abstract: Numerous embodiments are disclosed for an output circuit for an analog neural memory in a deep learning artificial neural network. In some embodiments, an output block receives current from a W+ bit line and current from an associated W? bit line, and the output block generates an output signal that is a differential signal in certain embodiments and is a single ended signal in other embodiments.

Abstract: Numerous examples are described for providing an artificial neural network system comprising an analog array and a digital array. In one example, an artificial neural network system comprises an analog array of non-volatile memory cells arranged into rows and columns; a digital array of non-volatile memory cells arranged into rows and columns, the analog array and the digital array fabricated on a same semiconductor die; a first plurality of bit lines, wherein each bit line in the first plurality of bit lines is coupled to a column of non-volatile memory cells in the analog array; and a second plurality of bit lines, wherein each bit line in the second plurality of bit lines is coupled to a column of non-volatile memory cells in the digital array and the second plurality of bit lines are disconnected from the first plurality of bit lines.

Abstract: In one example, a method comprises determining a bias voltage in response to a change in operating temperature of an array of non-volatile memory cells, each of the non-volatile memory cells in the array of memory cells comprising a control gate terminal and an erase gate terminal; and applying the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell in the array of memory cells while reading the selected memory cell.

Abstract: In one example, a system comprises an array of non-volatile memory cells arranged in rows and columns, wherein each non-volatile memory cell comprises a word line terminal and a bit line terminal; and a row circuit to receive a row address and a bias voltage and to output the bias voltage when the row address corresponds to a row of the array associated with the row circuit, wherein the bias voltage is provided to terminals of non-volatile memory cells in the row of the array associated with the row circuit.

Abstract: Numerous examples are disclosed of systems and methods to implement redundancy. In one example, a system comprises an array of non-volatile memory cells; a redundant array of non-volatile memory cells; and an input block coupled to respective rows in the array and respective rows in the redundant array and comprising row tag registers and redundant row tag registers.

Abstract: In one example, a system comprises an array of memory cells arranged in rows and columns, the array comprising bitlines coupled to respective columns in the array, respective bitlines comprising a sensing bitline metal layer and a current-carrying metal layer, wherein the sensing bitline metal layer does not carry current.

Abstract: Numerous examples are disclosed of systems and methods to implement redundancy. In one example, a system comprises an array of non-volatile memory cells; a redundant array of non-volatile memory cells; and an input block coupled to respective rows in the array and respective rows in the redundant array and comprising row tag registers and redundant row tag registers.

Abstract: Numerous embodiments of input circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.

Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an output block coupled to the vector-by-matrix multiplication array to receive current from the columns of the array, the output block comprising a current-to-voltage converter to receive current from one or two columns and convert the current into a voltage, the current-to-voltage converter comprising one or more variable resistors configurable to adjust the range of the voltage; and an analog-to-digital converter to convert the voltage into digital bits.

Abstract: In one example, a circuit comprises a current-to-voltage converter to convert a first current into a first voltage and to convert a second current into a second voltage, where the first current and the second current are differential currents; a level shifter to convert the first voltage into a third voltage and to convert the second voltage into a fourth voltage; and an analog-to-digital converter to convert the third voltage and the fourth voltage into a set of output bits.

Abstract: In one example, a system comprises a bitline regulation circuit comprising a first set of switches coupled to a bitline; and a second set of switches coupled to the bitline; wherein the bitline regulation circuit receives a first input from the first set of switches and a second input from the second set of switches, the first input comprising voltage and current and the second input comprising voltage and no current.

Abstract: Numerous examples are described for providing an artificial neural network system comprising an analog array and a digital array. In certain examples, an analog array and a digital array are coupled to shared bit lines. In other examples, an analog array and a digital array are coupled to separate bit lines.

Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to the source line of the array during operation.

Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.