Patents by Inventor Thuan Vu

Thuan Vu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240338144
    Abstract: Numerous examples are disclosed of a masking circuit for inputs and outputs in a neural network array. In one example, a system comprises a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent an application of a sparse input to one or more rows in the array when a condition is satisfied.
    Type: Application
    Filed: June 20, 2023
    Publication date: October 10, 2024
    Inventors: Hieu Van Tran, STEPHEN TRINH, HOA VU, STANLEY HONG, THUAN VU
  • Patent number: 12099921
    Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: September 24, 2024
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Stanley Hong, Anh Ly, Thuan Vu, Hien Pham, Kha Nguyen, Han Tran
  • Publication number: 20240312517
    Abstract: In one example, a method comprises erasing at the same time a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal, by turning on an erase gate enable transistor coupled to erase gate terminals of the word of non-volatile memory cells.
    Type: Application
    Filed: January 22, 2024
    Publication date: September 19, 2024
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Vipin Tiwari, Nhan Do
  • Patent number: 12075618
    Abstract: Numerous embodiments for reading or verifying a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input signals applied to a terminal of the selected memory cell, further resulting in a series of output signals that are digitized, shifted based on the bit location of the corresponding input bit in the set of input bits, and added to yield an output indicating a value stored in the selected memory cell.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: August 27, 2024
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Toan Le, Nghia Le, Hien Pham
  • Publication number: 20240282351
    Abstract: In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, the array comprising a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells; and an output block coupled to the array, the output block comprising: a current-to-voltage converter to convert a first current on the first bit line into a first voltage and to convert a second current on the second bit line into a second voltage; and an analog-to-digital converter to convert one or more of the first voltage and the second voltage into a set of output bits.
    Type: Application
    Filed: May 9, 2023
    Publication date: August 22, 2024
    Inventors: HIEU VAN TRAN, HOA VU, STEPHEN TRINH, STANLEY HONG, THUAN VU, NGHIA LE, DUC NGUYEN, HIEN PHAM
  • Publication number: 20240265951
    Abstract: In one example, a system comprises a current-to-voltage converter to generate differential voltages from differential currents comprising a first current and a second current, the current-to-voltage converter comprising: a first bitline to provide the first current; a second bitline to provide the second current; a first regulator to apply a first voltage to the first bitline; a second regulator to apply a second voltage to the second bitline; a regulating circuit comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first output terminal and the second output terminal providing the differential voltages; and a common mode circuit.
    Type: Application
    Filed: April 20, 2023
    Publication date: August 8, 2024
    Inventors: Hieu Van Tran, Hoa Vu, Stephen Trinh, Stanley Hong, Thuan Vu, Nghia Le, Duc Nguyen, Hien Pham
  • Patent number: 12057170
    Abstract: In one example, a system comprises a neural network array of non-volatile memory cells arranged in rows and columns; and a logical cell comprising a first plurality of non-volatile memory cells in a first row of the array and a second plurality of non-volatile memory cells in a second row adjacent to the first row; wherein the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells are configured as one or more coarse cells and one or more fine cells.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: August 6, 2024
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Stanley Hong, Stephen Trinh, Thuan Vu, Steven Lemke, Vipin Tiwari, Nhan Do
  • Publication number: 20240256146
    Abstract: Numerous examples are disclosed of systems and methods to implement redundancy. In one example, a system comprises an array of non-volatile memory cells; a redundant array of non-volatile memory cells; and an input block coupled to respective rows in the array and respective rows in the redundant array and comprising row tag registers and redundant row tag registers.
    Type: Application
    Filed: April 14, 2023
    Publication date: August 1, 2024
    Inventors: Hieu Van Tran, Thuan Vu, Kha Nguyen, Stephen Trinh, Stanley Hong, Hien Pham
  • Publication number: 20240256846
    Abstract: Numerous examples are disclosed of multiplexors coupled to rows in a neural network array. In one example, a system comprises a neural network array of non-volatile memory cells comprising i rows, where i is a multiple of 2; j row registers, where j<i; j digital-to-analog converters to convert j sets of digital data received from the j row registers into j analog signals; and j multiplexors to route the j analog signals to a subset of the i rows in response to a control signal.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 1, 2024
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly
  • Publication number: 20240127890
    Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 18, 2024
    Inventors: Hieu Van Tran, THUAN VU, STANLEY HONG, STEPHEN TRINH, ANH LY, NHAN DO, MARK REITEN
  • Publication number: 20240119272
    Abstract: In one example, a system comprises an analog neural memory array comprising a plurality of non-volatile memory cells arranged into rows and columns; and a voltage generator to provide a voltage to one or more rows of the analog neural memory array, the voltage generator comprising a voltage ladder to generate a plurality of voltages according to a logarithmic formula.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 11, 2024
    Inventors: HIEU VAN TRAN, THUAN VU, STANLEY HONG, STEPHEN TRINH, STEVEN LEMKE, LOUISA SCHNEIDER, NHAN DO
  • Publication number: 20240112729
    Abstract: Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.
    Type: Application
    Filed: December 6, 2022
    Publication date: April 4, 2024
    Inventors: Hieu Van TRAN, Stephen TRINH, Stanley HONG, Thuan VU, Anh LY, Fan LUO
  • Publication number: 20240112003
    Abstract: Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 4, 2024
    Inventors: HIEU VAN TRAN, STEPHEN TRINH, STANLEY HONG, THUAN VU, NGHIA LE, HIEN PHAM
  • Publication number: 20240112736
    Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to the source line of the array during operation.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 4, 2024
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly, Nhan Do, Mark Reiten
  • Publication number: 20240105263
    Abstract: In one example, a non-volatile memory system comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to a word line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the word line in response to changes in a voltage of the source line.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Applicant: Silicon Storage Technology, Inc.
    Inventors: Hieu Van TRAN, Thuan VU, Stanley HONG, Stephen TRINH, Anh LY, Nhan DO, Mark REITEN
  • Publication number: 20240104164
    Abstract: Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents, and a plurality of output blocks to receive current from respective columns of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication and generate digital outputs during a read operation of the vector-by-matrix multiplication.
    Type: Application
    Filed: December 13, 2022
    Publication date: March 28, 2024
    Inventors: HIEU VAN TRAN, STEPHEN TRINH, STANLEY HONG, THUAN VU, DUC NGUYEN, HIEN HO PHAM
  • Publication number: 20240104357
    Abstract: Numerous examples are disclosed of input circuitry and associated methods in an artificial neural network. In one example, a system comprises a plurality of address decoders to receive an address and output a plurality of row enabling signals in response to the address; a first plurality of registers to store, sequentially, activation data in response to the plurality of row enabling signals; and a second plurality of registers to store, in parallel, activation data received from the first plurality of registers.
    Type: Application
    Filed: December 8, 2022
    Publication date: March 28, 2024
    Inventors: Hieu Van Tran, Stephen Trinh, Stanley Hong, Thuan Vu, Nghia Le, Hien Pham
  • Publication number: 20240098991
    Abstract: In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Toan Le, Nghia Le, Hien Pham
  • Publication number: 20240095508
    Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells organized into rows and columns; a plurality of word lines coupled respectively to rows of the vector-by-matrix multiplication array; and a word line driver coupled to the plurality of word lines, the word line driver comprising a plurality of select transistors coupled to a common control line and the plurality of word lines, and a plurality of bias transistors coupled to the plurality of select transistors and capable of providing a bias voltage to a single select transistor in the plurality of select transistors or to all of plurality of select transistors in response to control signals.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: HIEU VAN TRAN, STANLEY HONG, AHN LY, THUAN VU, HIEN PHAM, KHA NGUYEN, HAN TRAN
  • Publication number: 20240095509
    Abstract: In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Hieu Van Tran, STANLEY HONG, ANH LY, THUAN VU, HIEN PHAM, KHA NGUYEN, HAN TRAN