Patents by Inventor Thuan Vu

Thuan Vu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PROGRAMMING ANALOG NEURAL MEMORY CELLS IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20210257026
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Application
    Filed: March 3, 2021
    Publication date: August 19, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Set-While-Verify Circuit And Reset-While Verify Circuit For Resistive Random Access Memory Cells
    Publication number: 20210257023
    Abstract: Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed. In one embodiment, a set-while-verify circuit for performing a set operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the set operation is complete. In another embodiment, a reset-while-verify circuit for performing a reset operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the reset operation is complete.
    Type: Application
    Filed: March 11, 2021
    Publication date: August 19, 2021
    Inventors: HIEU VAN TRAN, ANH LY, THUAN VU, STANLEY HONG, FENG ZHOU, XIAN LIU, NHAN DO
  • Decoders for analog neural memory in deep learning artificial neural network
    Patent number: 11087207
    Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 10, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Stanley Hong, Anh Ly, Thuan Vu, Hien Pham, Kha Nguyen, Han Tran
  • FLASH MEMORY CELL AND ASSOCIATED HIGH VOLTAGE ROW DECODER
    Publication number: 20210241839
    Abstract: The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.
    Type: Application
    Filed: April 23, 2021
    Publication date: August 5, 2021
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu
  • Programming circuit and method for flash memory array
    Patent number: 11069411
    Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: July 20, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • Programming Circuit and Method For Flash Memory Array
    Publication number: 20210210144
    Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.
    Type: Application
    Filed: September 17, 2019
    Publication date: July 8, 2021
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • Flash memory cell and associated high voltage row decoder
    Patent number: 11011240
    Abstract: The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: May 18, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu
  • INPUT AND DIGITAL OUTPUT MECHANISMS FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20210118894
    Abstract: Numerous embodiments for reading or verifying a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input signals applied to a terminal of the selected memory cell, further resulting in a series of output signals that are digitized, shifted based on the bit location of the corresponding input bit in the set of input bits, and added to yield an output indicating a value stored in the selected memory cell.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 22, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Toan Le, Nghia Le, Hien Pham
  • Programming Circuit and Method For Flash Memory Array
    Publication number: 20210082516
    Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • Current compensation block and method for programming analog neural memory in deep learning artificial neural network
    Patent number: 10943661
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: March 9, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • CHARGE PUMP FOR USE IN NON-VOLATILE FLASH MEMORY DEVICES
    Publication number: 20210035643
    Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 4, 2021
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Kha Nguyen, Hien Pham, Stanley Hong, Stephen T. Trinh
  • Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
    Publication number: 20210019608
    Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 21, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
  • Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
    Publication number: 20210020255
    Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 21, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
  • Analog neural memory system for deep learning neural network comprising multiple vector-by-matrix multiplication arrays and shared components
    Patent number: 10896368
    Abstract: Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network. In one embodiment, the analog neuromorphic memory system comprises a plurality of vector-by-matrix multiplication systems, each vector-by-matrix multiplication system comprising an array of memory cells, a low voltage row decoder, a high voltage row decoder, and a low voltage column decoder; a plurality of output blocks, each output block providing an output in response to at least one of the plurality of vector-by-matrix multiplication systems; and a shared verify block configured to concurrently perform a verify operation after a program operation on two or more of the plurality of vector-by-matrix systems.
    Type: Grant
    Filed: January 18, 2020
    Date of Patent: January 19, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly
  • Analog neural memory system for deep learning neural network comprising multiple vector-by-matrix multiplication arrays and shared components
    Patent number: 10860918
    Abstract: Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network. The analog neuromorphic memory system comprises a plurality of vector-by-matrix multiplication arrays and various components shared by those arrays. The shared components include high voltage generation blocks, verify blocks, and testing blocks. The analog neuromorphic memory system optionally is used within a long short term memory system or a gated recurrent unit system.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: December 8, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly
  • Charge pump for use in non-volatile flash memory devices
    Patent number: 10847227
    Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 24, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Kha Nguyen, Hien Pham, Stanley Hong, Stephen T. Trinh
  • Dynamic modification of programming duration based on number of cells to be programmed in analog neural memory array in deep learning artificial neural network
    Patent number: 10839907
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, the duration of a programming voltage can change as the number of cells to be programmed changes.
    Type: Grant
    Filed: August 24, 2019
    Date of Patent: November 17, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • CONFIGURABLE INPUT BLOCKS AND OUTPUT BLOCKS AND PHYSICAL LAYOUT FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20200349421
    Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.
    Type: Application
    Filed: June 21, 2019
    Publication date: November 5, 2020
    Inventors: Hieu Van Tran, STEPHEN TRINH, THUAN VU, STANLEY HONG, VIPIN TIWARI, MARK REITEN, NHAN DO
  • OUTPUT ARRAY NEURON CONVERSION AND CALIBRATION FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20200349422
    Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks. Systems and methods are utilized for compensating for leakage and offset in the input blocks and output blocks the in analog neural memory systems.
    Type: Application
    Filed: June 21, 2019
    Publication date: November 5, 2020
    Inventors: Hieu Van Tran, Stephen Trinh, Thuan Vu, Stanley Hong, Vipin Tiwari, Mark Reiten, Nhan Do
  • DECODING SYSTEM AND PHYSICAL LAYOUT FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20200342938
    Abstract: Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 29, 2020
    Inventors: HIEU VAN TRAN, THUAN VU, STANLEY HONG, STEPHEN TRINH, ANH LY, HAN TRAN, KHA NGUYEN, HIEN PHAM