Abstract: A low latency cache intervention mechanism implements a snoop filter to dynamically select an intervener cache for a cache “hit” in a multiprocessor architecture of a computer system. The selection of the intervener is based on variables such as latency, topology, frequency, utilization, load, wear balance, and/or power state of the computer system.

Abstract: Counter registers are shared among multiple threads executing on multiple processor cores. An event within the processor core is selected. A multiplexer in front of each of a number of counters is configured to route the event to a counter. A number of counters are assigned for the event to each of a plurality of threads running for a plurality of applications on a plurality of processor cores, wherein each of the counters includes a thread identifier in the interrupt thread identification field and a processor identifier in the processor identification field. The number of counters is configured to have a number of interrupt thread identification fields and a number of processor identification fields to identify a thread that will receive a number of interrupts.

Abstract: A number of hypervisor register fields are set to specify which processor cores are allowed to generate a number of performance events for a particular thread group. A plurality of threads for an application running in the computing environment to a plurality of thread groups are configured by a plurality of thread group fields in a plurality of control registers. A number of counter sets are allowed to count a number of thread group events originating from one of a shared resource and a shared cache are specified by a number of additional hypervisor register fields.

Abstract: Sampled instruction address registers are shared among multiple threads executing on a plurality of processor cores. Each of a plurality of sampled instruction address registers are assigned to a particular thread running for an application on the plurality of processor cores. Each of the sampled instruction address registers are configured by storing in each of the sampled instruction address registers a thread identification of the particular thread in a thread identification field and a processor identification of a particular processor on which the particular thread is running in a processor identification field.

Abstract: A number of hypervisor register fields are set to specify which processor cores are allowed to generate a number of performance events for a particular thread group. A plurality of threads for an application running in the computing environment to a plurality of thread groups are configured by a plurality of thread group fields in a plurality of control registers. A number of counter sets are allowed to count a number of thread group events originating from one of a shared resource and a shared cache are specified by a number of additional hypervisor register fields.

Abstract: Sampled instruction address registers are shared among multiple threads executing on a plurality of processor cores. Each of a plurality of sampled instruction address registers are assigned to a particular thread running for an application on the plurality of processor cores. Each of the sampled instruction address registers are configured by storing in each of the sampled instruction address registers a thread identification of the particular thread in a thread identification field and a processor identification of a particular processor on which the particular thread is running in a processor identification field.

Abstract: Counter registers are shared among multiple threads executing on multiple processor cores. An event within the processor core is selected. A multiplexer in front of each of a number of counters is configured to route the event to a counter. A number of counters are assigned for the event to each of a plurality of threads running for a plurality of applications on a plurality of processor cores, wherein each of the counters includes a thread identifier in the interrupt thread identification field and a processor identifier in the processor identification field. The number of counters is configured to have a number of interrupt thread identification fields and a number of processor identification fields to identify a thread that will receive a number of interrupts.

Abstract: A system for communicating command parameters between a processor and a memory flow controller is provided. The system makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A method for communicating instructions and data between a processor and external devices are provided. The method makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A method and system for creating trace triggers from non-concurrent events, the system comprising: a trace trigger mechanism including: a plurality of multiplexers for breaking down a plurality of signals into a plurality of groups of signals; a pattern match mechanism for matching the plurality of signals to form a plurality of events, and a trace array trigger control block to perform one or more functions on the plurality of independently controlled events in order to create flexible trace trigger controls from non-concurrent events to control the starting and stopping of a data gathering function such as is used to capture trace data.

Abstract: A system and method for reducing store latency in symmetrical multiprocessor systems are provided. Bus agents are provided which monitor reflected ownership requests (Dclaims) to determine if the reflected Dclaim is its own Dclaim. If so, the bus agent determines that it is the winner of the ownership request and can immediately perform data modification using its associated local cache. If the bus agent determines that the reflected Dclaim does not match its own Dclaim, it determines that it is the loser of the ownership request and invalidates the corresponding cache line in its own local cache. The loser bus agent may then send a Read With Intent to Modify request to obtain the data from another cache and place it into its own cache for modification. These operations are performed without the need for a Kill request and without having to perform retries of a losing ownership request.

Abstract: The present invention utilizes the good qualities of a single address concentrator (AC), without any extra chips or wires, and distributes the AC function among the various chips, making use of the fact that each chip in the system has a copy of the AC function therein. Using the distributed address concentrator function, each chip will handle approximately one-fourth of the command traffic and the average latency of servicing the commands will be approximately the same across each chip in the system.

Abstract: A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A method and system for creating trace triggers from non-concurrent events, the system comprising: a trace trigger mechanism including: a plurality of multiplexers for breaking down a plurality of signals into a plurality of groups of signals; a pattern match mechanism for matching the plurality of signals to form a plurality of events, and a trace array trigger control block to perform one or more functions on the plurality of independently controlled events in order to create flexible trace trigger controls from non-concurrent events to control the starting and stopping of a data gathering function such as is used to capture trace data.

Abstract: A system and method for reducing store latency in symmetrical multiprocessor systems are provided. Bus agents are provided which monitor reflected ownership requests (Dclaims) to determine if the reflected Dclaim is its own Dclaim. If so, the bus agent determines that it is the winner of the ownership request and can immediately perform data modification using its associated local cache. If the bus agent determines that the reflected Dclaim does not match its own Dclaim, it determines that it is the loser of the ownership request and invalidates the corresponding cache line in its own local cache. The loser bus agent may then send a Read With Intent to Modify request to obtain the data from another cache and place it into its own cache for modification. These operations are performed without the need for a Kill request and without having to perform retries of a losing ownership request.

Abstract: A system having a plurality of arbitration levels for detecting and breaking up requester starvation, the system including: a plurality of logic circuits, each of the plurality of logic circuits permitted to access a cache via a plurality of requesters for requesting information from the cache; a counter for counting a number of times each of the plurality of requesters of each of the plurality of logic circuits has successfully accessed one or more of the plurality of arbitration levels and has been rejected by a subsequent arbitration level; wherein if the counter reaches a predetermined threshold for a requester of a logic circuit, the counter triggers an event that increases a priority level of the requester compared to all other requesters attempting to access the cache, so that the requestor reaches the cache before the other requesters.

Abstract: A system for breaking out of live-locks, the system including: a plurality of central processing units (CPUs), each of the plurality of CPUs having a first level cache; a plurality of second level cache, each of the plurality of second level cache in communication with one or more of the plurality of CPUs; wherein each of the plurality of second level cache includes a plurality of DMs (Data Machines); and wherein the system executes the communication between the plurality of CPUs and the plurality of second level cache by implementing the steps: randomly stopping dispatching of one or more requests; verifying that the plurality of DMs of the second level cache is in an idle state; entering into a single dispatch mode, whereby a DM is dispatched if it is determined that every DM of the second level cache is in the idle state; and returning to normal dispatch mode in a random manner.