Abstract: A system for detecting and breaking up requester starvation, including: a plurality of logic circuits, each of the plurality of logic circuits permitted to access a cache via a plurality of requesters for requesting information from the cache; and a counter for counting a number of times each of the plurality of requestors of each of the plurality of logic circuits has (i) successfully accessed one or more of a plurality of arbitration levels and (ii) has been rejected by a subsequent arbitration level; wherein when the counter reaches a predetermined threshold value, an event is triggered to block a first type of requester from accessing the cache and to permit a second type of requester to access the cache; and wherein the counter is reconfigured to count a predetermined number of cycles before the first type of requester is unblocked from accessing the cache.

Abstract: A memory management unit (MMU) performs address translation and protection using a segment table and page table model. Each DMA queue entry may include a MMU-miss dependency flag. The DMA issue mechanism uses the MMU-miss dependency flag to block the issue of commands that are known to result in a translation miss. However, the direct memory access engine does not block subsequent DMA commands from being issued until they receive a translation miss. When the MMU completes processing of a miss, the MMU sends a miss clear signal to the DMA control unit to reset all MMU-miss dependency flags. When the MMU sends a miss clear signal, the DMA control unit will reset all DMA queue entries with MMU-miss dependency flags set. DMA commands in the DMA queue that were blocked from issue by the MMU-miss dependency flag may now be selected by the DMA control unit for issue.