Abstract: This disclosure relates to a baseband processor for processing down-converted and quantized radio frequency, RF, signals of an RF transceiver in baseband, wherein the baseband processor is configured to: detect an RF operation mode switching of the RF transceiver, and initiate a change of a voltage setting and an associated system clock rate of the baseband processor based on detecting the operation mode switching of the RF transceiver.

Abstract: Embodiments include apparatuses, methods, and systems for determining a power consumption of a circuit block in an integrated circuit. The integrated circuit may include first and second power supply networks. In some embodiments, the integrated circuit may include a plurality of instances of a circuit block under test. A first instance of the circuit block may be coupled to the first power supply network during a first test run, and a second instance of the circuit block may be coupled to the second power supply network during a second test run. In other embodiments, a single instance of a circuit block under test may be coupled with the first power supply network during a first test run and coupled with the second power supply network during a second test run. The power consumption of the circuit block may be determined based on the first and second test runs.

Abstract: Embodiments include apparatuses, methods, and systems for determining a power consumption of a circuit block in an integrated circuit. The integrated circuit may include first and second power supply networks. In some embodiments, the integrated circuit may include a plurality of instances of a circuit block under test. A first instance of the circuit block may be coupled to the first power supply network during a first test run, and a second instance of the circuit block may be coupled to the second power supply network during a second test run. In other embodiments, a single instance of a circuit block under test may be coupled with the first power supply network during a first test run and coupled with the second power supply network during a second test run. The power consumption of the circuit block may be determined based on the first and second test runs.

Abstract: An apparatus and method are described for performing a low overhead error checking and correction. For example, one embodiment of an electronic circuit comprises: one or more memories to store data or instructions in rows and columns, and to further store row parity data comprising a parity value associated with each row and column parity data comprising a parity value associated with each column; and error checking logic to perform a row parity check to detect if errors exist in any of the rows, wherein if an error is detected in one of the rows, the error checking and correction logic is to perform a column parity check to identify a column in which the detected error occurred; and error correction logic to correct the detected error using the detected row and column identified by the error checking logic.

Abstract: Embodiments are described that provide methods and radio networks that communicate data between a mobile communication device and a core network. The methods include using network coding to encode data, and communicating a subset of the encoded data between the mobile communication device and the core network through a dynamic relay station.

Abstract: Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function.

Abstract: A method is provided for switching between two oscillator signals within an alignment element. In accordance with the method, one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. The method comprises introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected. The method further comprises sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed.

Abstract: The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits (18, 20, 22, 24) and storage elements (14, 16) connected serially to a number of LBIST stumps (10, 12) between a pseudo-random-pattern generator (26) and a multiple-input-signature register (28), wherein at least one constrained logic circuit (18) requires constrained values as input signals.

Abstract: A method for performing a test case with at least one LBIST engine on an integrated circuit with a plurality of storage elements and logic circuits interconnected according to a predetermined scheme. The LBIST engine is partially built up by storage elements and/or logic circuits. At least one scan chain is formed as a series of selected storage elements and the other storage elements are used for the LBIST engine or a part of said LBIST engine in a testing mode. The scan chain is driven by a test pattern and the LBIST test case is testing those parts of the logic circuits corresponding to the storage elements of said scan chain.

Abstract: An integrated circuit on a semiconductor chip with a plurality of registers distributed across the semiconductor chip. The registers are writeable and readable. The integrated circuit comprises a central control block. The integrated circuit comprises a plurality of circuit units. The circuit unit includes a functional portion with a local clock controller and one or more of the registers. The circuit unit includes a satellite portion. The central control block and the satellite portions are serially connected together and form a scan chain, wherein the scan chain is formed as a ring.

Abstract: The various embodiments described herein relate to a system for performing a serial communication between a central control block and a plurality of satellite components within a semiconductor chip. The system comprises at least one logical ring that serially connects the satellite components to the central control block. The system further comprises a centralized timer. The satellite components aid the system in obeying protocols and performing direct accesses to and/or from registers. The logical ring comprises at least one data channel that is provided for transmitting data packets and address packets. Single-envelope transactions are implemented. Errors of the satellite components associated with the single-envelope transactions are reported to the central control block as additional acknowledgement information.

Abstract: The processing of tasks in a mobile communication terminal that contains two or more microprocessors is disclosed. The processing rate of tasks is increased by redistribution of the tasks between the microprocessors as a function of the operating mode. Particularly in situations in which no conversation and/or no other type of payload signal transmission is taking place, tasks may be redistributed from the application processor to the modem processor and/or to the DSP, so that applications such as compression and/or decompression of video data can be processed more quickly.

Abstract: Embodiments are described that provide methods and radio networks that communicate data between a mobile communication device and a core network. The methods include using network coding to encode data, and communicating a subset of the encoded data between the mobile communication device and the core network through a dynamic relay station.

Abstract: The apparatus contains a counter that is synchronized to the reference time in the mobile station. The counter counts sampled chips of the radio signal to produce a count. The apparatus further includes a controller that controls the processing of the radio signal, activates the processing of the radio signal when the count matches a begin count, and deactivates the processing of the radio signal when the count matches an end count, wherein the begin count and the end count are determined by a signal processor as a function of the time frame offset of the radio signal with respect to the reference time in the mobile station.

Abstract: A method, structure and design system for performing logic built-in-self-test (LBIST) cycles on a semiconductor chip with a plurality of logic circuits and a plurality of storage elements connected serially to a number of LBIST stumps (pattern segments) between a pseudo-random-pattern generator (30) and a multiple-input-signature register. The semiconductor chip is subdivided into partitions, such that LBIST cycles may be run separately or in parallel for one or more partitions. The LBIST cycles may also be run separately or in parallel inter-connections between the partitions. The partitions to be tested are controlled by at least one corresponding clock signal, and the inter-connections to be tested are controlled by at least one corresponding clock signal.

Abstract: The various embodiments described herein relate to a system for performing a serial communication between a central control block and a plurality of satellite components within a semiconductor chip. The system comprises at least one logical ring that serially connects the satellite components to the central control block. The system further comprises a centralized timer. The satellite components aid the system in obeying protocols and performing direct accesses to and/or from registers. The logical ring comprises at least one data channel that is provided for transmitting data packets and address packets. Single-envelope transactions are implemented. Errors of the satellite components associated with the single-envelope transactions are reported to the central control block as additional acknowledgement information.

Abstract: In a method for carrying out a plurality of correlation procedures in a mobile radio system, sample values which have been written to a data memory (DS) are read using a predetermined reading rule. Two correlation procedures are carried out on the basis of the sample values which have been read. This reading rule is in this case independent of the correlation procedure to be carried out.

Abstract: A method for switching between two oscillator signals within an alignment element, wherein one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. Said method comprises the steps of: introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected; sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed; sending the virtual stepping signal to the output of the alignment element in the event of a failure in the master signal until a switch to the other oscillator signal as a new master signal is performed or until the first master signal becomes valid again.

Abstract: A method for synchronization of a mobile radio receiver having a time slot structure for a radio signal is disclosed. A data stream received by the mobile radio receiver is filtered in a filter, thereby producing a decision sequence of received data as a set of maximum possible determined time slot boundaries. The decision sequence is processed in a two-step method such that, in a first method step, a subset is selected from the decision sequence and, then, in a second method step, the elements of said subset are averaged over time, with the time slot boundary which is used for synchronization being obtained as the result of this averaging process. In this case, the subset is selected using statistical characteristics of those signal sample values that are associated with a time slot boundary, and of those signal sample values which are not associated with a time slot boundary.

Abstract: In a method for synchronization of a receiver to a transmitter which periodically transmits a sequence which is known in the receiver, a subset of possible synchronization times is determined in a first selection process by repeated correlation of the received signal with the known sequence and comparison of the correlation responses, as calculated for the correlations, with a threshold value. The threshold value is in this case varied adaptively as a function of at least one parameter which is measured during the correlations.