Abstract: A method to resolve a deadlock in a bus architecture comprising a first and a second single-envelope bus with at least one master and one slave each, where the first and second single-envelope buses are arranged on different sides of an asynchronous boundary and are coupled via a bus bridge, said method comprising the steps of: granting the bus to a first master arranged on a first side of the asynchronous boundary which requests a transaction within a critical time window; monitoring the bus which has been granted for transaction to the first master; stealing silently the bus from the first master if a deadlock condition arises; granting the bus to a second master arranged on a second side of the asynchronous boundary raising the deadlock condition by requesting a second transaction within the critical time window; completing the second transaction to resolve the deadlock scenario; and returning back the bus to the first master to complete the first transaction.

Abstract: An integrated circuit on a semiconductor chip with a plurality of registers distributed across the semiconductor chip. The registers are writeable and readable. The integrated circuit comprises a central control block. The integrated circuit comprises a plurality of circuit units. The circuit unit includes a functional portion with a local clock controller and one or more of the registers. The circuit unit includes a satellite portion. The central control block and the satellite portions are serially connected together and form a scan chain, wherein the scan chain is formed as a ring.

Abstract: The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits (18, 20, 22, 24) and storage elements (14, 16) connected serially to a number of LBIST stumps (10, 12) between a pseudo-random-pattern generator (26) and a multiple-input-signature register (28), wherein at least one constrained logic circuit (18) requires constrained values as input signals.

Abstract: Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function.

Abstract: The present invention relates to a method for arbitrating requests from masters to grant access to shared resources, wherein each master has an individual weight. The method comprises the steps of assigning time slots to the masters depending on the weights of the masters, mapping the current time slot index (32) to a reordering index (30), receiving a plurality of requests from N masters, reordering the requests into a request vector (14) depending on the reordering index (30), searching for predetermined logical values in the request vector (14), generating a grant vector (18) according to the index of the found logical values in the request vector (14), inversely reordering the grant vector (18) into an output grant vector (22) depending on the reordering index (30), and calculating a new time slot index (32) on the basis of the current time slot index (30) and the grant vector (18). Further the present invention relates to a system for performing the method.

Abstract: The present invention relates to a method for performing a test case with at least one LBIST engine on an integrated circuit with a plurality of storage elements and logic circuits interconnected according to a predetermined scheme. The LBIST engine is at least partially built up by storage elements and/or logic circuits. At least one scan chain is formed as a series of selected storage elements and the other storage elements are used for the LBIST engine or a part of said LBIST engine in a testing mode. The scan chain is driven by a test pattern and the LBIST test case is testing those parts of the logic circuits corresponding to the storage elements of said scan chain.

Abstract: A transmission/reception device for mobile radio applications has a microprocessor (DSP), at least one task-specific processor (P1, P2, P3) and a processor interface (2). The task-specific processor (P1, P2, P3) can be configured, by transmitting suitable configuration instructions from the microprocessor via the processor interface (2), such that a basic function performed by the task-specific processor (P1, P2, P3) can be controlled by changing configuration parameters.

Abstract: In a method for carrying out a plurality of correlation procedures in a mobile radio system, sample values which have been written to a data memory (DS) are read using a predetermined reading rule. Two correlation procedures are carried out on the basis of the sample values which have been read. This reading rule is in this case independent of the correlation procedure to be carried out.

Abstract: A method for synchronization of a mobile radio receiver having a time slot structure for a radio signal is disclosed. A data stream received by the mobile radio receiver is filtered in a filter, thereby producing a decision sequence of received data as a set of maximum possible determined time slot boundaries. The decision sequence is processed in a two-step method such that, in a first method step, a subset is selected from the decision sequence and, then, in a second method step, the elements of said subset are averaged over time, with the time slot boundary which is used for synchronization being obtained as the result of this averaging process. In this case, the subset is selected using statistical characteristics of those signal sample values that are associated with a time slot boundary, and of those signal sample values which are not associated with a time slot boundary.

Abstract: In a method for synchronization of a receiver to a transmitter which periodically transmits a sequence which is known in the receiver, a subset of possible synchronization times is determined in a first selection process by repeated correlation of the received signal with the known sequence and comparison of the correlation responses, as calculated for the correlations, with a threshold value. The threshold value is in this case varied adaptively as a function of at least one parameter which is measured during the correlations.

Abstract: A device (11) for carrying out a correlation, having a data memory (12) for storage of a sequence of sample values (110), having an address generator (13) for production of addresses for reading a data word (111), in which the sequence of sample values in the data word (111) need not be chronological, having a code generator (15) for production of a correlation word (112) from sequence elements in a correlation sequence, with the sequence elements being arranged in the correlation word (112) in a sequence which depends on the data word (111), and having a correlator unit (14).

Abstract: The processing of tasks in a mobile communication terminal that contains two or more microprocessors is disclosed. The processing rate of tasks is increased by redistribution of the tasks between the microprocessors as a function of the operating mode. Particularly in situations in which no conversation and/or no other type of payload signal transmission is taking place, tasks may be redistributed from the application processor to the modem processor and/or to the DSP, so that applications such as compression and/or decompression of video data can be processed more quickly.

Abstract: The apparatus contains a counter that is synchronized to the reference time in the mobile station. The counter counts sampled chips of the radio signal to produce a count. The apparatus further includes a controller that controls the processing of the radio signal, activates the processing of the radio signal when the count matches a begin count, and deactivates the processing of the radio signal when the count matches an end count, wherein the begin count and the end count are determined by a signal processor as a function of the time frame offset of the radio signal with respect to the reference time in the mobile station.

Abstract: A transmission/reception device for mobile radio applications has a microprocessor (DSP), at least one task-specific processor (P1, P2, P3) and a processor interface (2). The task-specific processor (P1, P2, P3) can be configured, by transmitting suitable configuration instructions from the microprocessor via the processor interface (2), such that a basic function performed by the task-specific processor (P1, P2, P3) can be controlled by changing configuration parameters.

Abstract: A device (1) for accelerated synchronization of a mobile radio receiver to a frame structure of a received radio signal, comprises a unit (2) to determine energy values that were received by the mobile radio receiver for each frame synchronization code per time slot, at least two intermediate memories (TEMP_RAM_EVEN, TEMP_RAM_ODD) to store the energy values and a unit (PEAK_DETECT, 3) to calculate the frame start of the radio signal from the energy values and the known frame synchronization codes.