Patents by Inventor Thy Tran

Thy Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9911653
    Abstract: Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of manufacturing an interconnect structure includes forming an opening in a surface of a semiconductor device and forming an interconnect structure at least within the opening. Forming the interconnect structure includes depositing a first insulator material on both the surface and a sidewall of the opening, selectively removing a first portion of the first insulator material on the surface over a second portion of the first insulator material on the sidewall, depositing a second insulator material on the second portion, and depositing a conductive material on the second insulator material. The method further includes selecting the thickness of the first and second insulators materials based on a threshold level of capacitance between the sidewall and the conductive material.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jin Lu, Hongqi Li, Kevin Torek, Thy Tran, Alex Schrinsky
  • Publication number: 20170162440
    Abstract: Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of manufacturing an interconnect structure includes forming an opening in a surface of a semiconductor device and forming an interconnect structure at least within the opening. Forming the interconnect structure includes depositing a first insulator material on both the surface and a sidewall of the opening, selectively removing a first portion of the first insulator material on the surface over a second portion of the first insulator material on the sidewall, depositing a second insulator material on the second portion, and depositing a conductive material on the second insulator material. The method further includes selecting the thickness of the first and second insulators materials based on a threshold level of capacitance between the sidewall and the conductive material.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Inventors: Jin Lu, Hongqi Li, Kevin Torek, Thy Tran, Alex Schrinsky
  • Patent number: 9613864
    Abstract: Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of manufacturing an interconnect structure includes forming an opening in a surface of a semiconductor device and forming an interconnect structure at least within the opening. Forming the interconnect structure includes depositing a first insulator material on both the surface and a sidewall of the opening, selectively removing a first portion of the first insulator material on the surface over a second portion of the first insulator material on the sidewall, depositing a second insulator material on the second portion, and depositing a conductive material on the second insulator material. The method further includes selecting the thickness of the first and second insulators materials based on a threshold level of capacitance between the sidewall and the conductive material.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: April 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Jin Lu, Hongqi Li, Kevin Torek, Thy Tran, Alex Schrinsky
  • Publication number: 20160111372
    Abstract: Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of manufacturing an interconnect structure includes forming an opening in a surface of a semiconductor device and forming an interconnect structure at least within the opening. Forming the interconnect structure includes depositing a first insulator material on both the surface and a sidewall of the opening, selectively removing a first portion of the first insulator material on the surface over a second portion of the first insulator material on the sidewall, depositing a second insulator material on the second portion, and depositing a conductive material on the second insulator material. The method further includes selecting the thickness of the first and second insulators materials based on a threshold level of capacitance between the sidewall and the conductive material.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 21, 2016
    Inventors: Jin Lu, Hongqi Li, Kevin Torek, Thy Tran, Alex Schrinsky
  • Patent number: 8871103
    Abstract: A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: October 28, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Brett Busch, Gowri Damarla, Anurag Jindal, Chia-Yen Ho, Thy Tran
  • Publication number: 20140231894
    Abstract: A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.
    Type: Application
    Filed: April 30, 2014
    Publication date: August 21, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Kunal Parekh, Ceredig Roberts, Thy Tran, Jim Jozwiak, David Hwang
  • Patent number: 8716116
    Abstract: A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: May 6, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kunal Parekh, Ceredig Roberts, Thy Tran, Jim Jozwiak, David Hwang
  • Publication number: 20140038414
    Abstract: A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.
    Type: Application
    Filed: October 9, 2013
    Publication date: February 6, 2014
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: BRETT BUSCH, GOWRI DAMARLA, ANURAG JINDAL, Chia-Yen Ho, THY TRAN
  • Patent number: 8580690
    Abstract: A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: November 12, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Brett Busch, Gowri Damarla, Anurag Jindal, Chia-Yen Ho, Thy Tran
  • Publication number: 20120258596
    Abstract: A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.
    Type: Application
    Filed: April 6, 2011
    Publication date: October 11, 2012
    Inventors: BRETT BUSCH, GOWRI DAMARLA, ANURAG JINDAL, CHIA-YEN HO, THY TRAN
  • Publication number: 20110220994
    Abstract: A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.
    Type: Application
    Filed: March 10, 2010
    Publication date: September 15, 2011
    Applicant: Micron Technology, Inc.
    Inventors: Kunal Parekh, Ceredig Roberts, Thy Tran, Jim Jozwiak, David Hwang