Abstract: A low-power-consumption actuator for battery-powered electronic lock includes assembled first and second cases, the second case being provided at a top with a through bore; a piezoceramic/steel sheet assembly consisting of superposed first and second piezoceramic/steel sheet sets, a first end portion of the second piezoceramic/steel sheet set being in a free state; a circuit board electrically connected to the piezoceramic/steel sheet assembly; and a pin unit being located between a top of the first end portion of the second piezoceramic/steel sheet set and the through bore. When the circuit board applies a voltage across the piezoceramic/steel sheet assembly, the first end portion of the second piezoceramic/steel sheet set upward flexes and thereby displaces to push against the pin unit for a pin thereof to protrude from the through bore and interfere with a latch bolt of the electronic lock, so as to actuate the latch bolt.

Abstract: A transparent speaker is suitable for being disposed on a display panel. The transparent speaker includes a transparent membrane, a transparent electrode plate, and spacers. Each transparent electrode plate has a plurality of openings. The display panel includes a plurality of pixels. The pixels emit optical signals. A Moire spatial period of the optical signals is less than 600 ?m after the optical signals pass through the transparent speaker. When the transparent speaker is disposed on the display panel, a user is able to watch an image on the display panel through the transparent speaker without being interfered by a Moire.

Abstract: A semiconductor package with a substrate ID code and its manufacturing method are revealed. A circuit and a solder mask are formed on the bottom surface of a substrate where the solder mask covers most of the circuit and a circuit-free zone of the substrate. A chip is disposed on the top surface of the substrate. A substrate ID code consisting of a plurality of laser marks is inscribed in the solder mask or in a portion of an encapsulant on the bottom surface away from the circuit to show the substrate lot number on the bottom surface. Therefore, quality control and failure tracking and management can easily be implemented by tracking the substrate ID code from the semiconductor package without changing the appearance of the semiconductor package. Furthermore, the substrate ID code can be implemented by the existing laser imprinting machines for semiconductor packaging processes and be formed at the same time of formation of a product code.

Abstract: A photoelectric converting device which includes a substrate layer and an active layer is proposed. The active layer, which is disposed over the substrate layer, has a light receiving surface with a textured structure. The textured structure includes multiple indented units and each of the indented units includes three planes, which form an indentation tip at the intersection point between the three planes. The three planes are perpendicular or about perpendicular to each other.

Abstract: The present invention provides an optical head with a single or multiple sub-wavelength light beams, which can be used in arenas such as photolithography, optical storage, optical microscopy, to name a few. The present invention includes a transparent substrate, a thin film, and a surface structure with sub-wavelength surface profile. The incident light transmits through the transparent substrate, forms a surface plasma wave along the sub-wavelength aperture located within the thin film, and finally re-emits through spatial coupling with the sub-wavelength profile of the surface structure. As the coupled re-emitting light beam or light beams can maintain the waist less than that of the diffraction limit for a few micrometers out of the surface with sub-wavelength profile in many cases, this invention can have applications ranging from micro or nano manufacturing, metrology, and manipulation by using light beams with waist smaller than the diffraction limit.

Abstract: A WBGA semiconductor package primarily comprises a substrate, a chip, a chip-bonding adhesive, a plurality of bonding wires electrically connecting the chip and the substrate, an encapsulant to encapsulate the chip and the bonding wires, and a plurality of external terminals disposed under the substrate. The substrate has a depression for accommodating the chip-bonding adhesive and a slot for passing through bonding wires. The chip is partially embedded in the depression to dispose on the substrate. During the chip bonding step, the chip-bonding adhesive is confined in the depression in a manner to fill the gaps between the sides of the first chip and the inwalls around the depression to generate a non-planar adhering interface by partially covering the sides of the first chip. Therefore, the total package thickness is reduced, the delamination of the passivation layer and the fractures at the sides of the chip are avoided.

Abstract: A router and a method for avoiding the IP address conflict are disclosed. The method includes the following steps. First, once the router obtains an IP address as its WAN IP address, the network bits of the WAN IP address and the network bits of an IP pool of the router are retrieved. Then, it follows to determine whether the network bits of the WAN IP address is identical to that of the IP pool, and if yes, modify the network bits of the IP pool together with a LAN IP address of the router to be different from that of the WAN IP address. After that, an instruction is transmitted to the client terminals associated with the router. Upon reception of the instruction, the client terminals replace the old IP addresses with the new IP addresses assigned from the router in accordance with Dynamic Host Configuration Protocol.

Abstract: A WBGA semiconductor package primarily comprises a substrate, a chip, a chip-bonding adhesive, a plurality of bonding wires electrically connecting the chip and the substrate, an encapsulant to encapsulate the chip and the bonding wires, and a plurality of external terminals disposed under the substrate. The substrate has a depression for accommodating the chip-bonding adhesive and a slot for passing through bonding wires. The chip is partially embedded in the depression to dispose on the substrate. During the chip bonding step, the chip-bonding adhesive is confined in the depression in a manner to fill the gaps between the sides of the first chip and the inwalls around the depression to generate a non-planar adhering interface by partially covering the sides of the first chip. Therefore, the total package thickness is reduced, the delamination of the passivation layer and the fractures at the sides of the chip are avoided.

Abstract: A light diffusion module and a back light module using the same. The light diffusion module is disposed corresponding to the light source module of the back light module. The light diffusion module includes a first diffusion layer and the second diffusion layer. The first diffusion layer is disposed on top of the light source module and the top light exit surface has a plurality of first micro structures juxtapositioned to each other. The second diffusion layer is disposed on top of the first diffusion layer, and the top surface has a plurality of second micro structures juxtapositioned to each other. The ratio of the width of each first micro structure to the width of each second micro structure is between 1.1 and 1.8. The ratio of the height of each first micro structure to the height of each second micro structure is between 0.8 and 1.5.

Abstract: A light diffusion module and a back light module using the same. The light diffusion module is disposed corresponding to the light source module of the back light module. The light diffusion module includes a first diffusion layer and the second diffusion layer. The first diffusion layer is disposed on top of the light source module and the top light exit surface has a plurality of first micro structures juxtapositioned to each other. The second diffusion layer is disposed on top of the first diffusion layer, and the top surface has a plurality of second micro structures juxtapositioned to each other. The ratio of the width of each first micro structure to the width of each second micro structure is between 1.1 and 1.8. The ratio of the height of each first micro structure to the height of each second micro structure is between 0.8 and 1.5.

Abstract: The present invention discloses a method for fabricating semiconductor elements, which comprises steps: providing a substrate having a wiring pattern on the upper surface thereon electrically connecting a wafer to the substrate for signal input and output; filling a resin into between the wafer and tire substrate to fix the wafer to the substrate; and singulating the combination of the wafer and the substrate into a plurality of semiconductor elements. Therefore, the present can simplify the fabrication process or semiconductor elements.

Abstract: The present invention discloses a lead frame and chip package structure, which comprises a plurality of leads including a plurality of inner leads and a plurality of outer leads; a plurality of chips arranged on a portion of the inner leads; a plurality of connecting wires electrically connecting the chips to the other inner leads; a support member arranged on the lower surface of the inner leads and having a fillister with an opening, wherein the backside of the opening faces the inner leads; and a resin encapsulant covering the leads, the chips, the connecting wires and the support member, and filling up the fillister with a portion of the outer leads and a portion of the surface of the support member being revealed. Further, the present invention also discloses a method for fabricating a lead frame and chip package structure, whereby the quality of a chip package is promoted.

Abstract: A chip mounting device includes at least one chip mounting unit and at least one side rail configured beside the chip mounting unit. The chip mounting unit includes a die pad and a plurality of conductive contacts. The side rail includes at least one identifying element. A chip package array with the above-mentioned chip mounting device is also disclosed. The chip mounting device and chip package array includes the identifying element configured on the side rail to improve the identification of semi-finished packaged chips during chip package process to be read automatically by machines instead of operators, and further decrease the loss caused by misjudgments of operators.

Abstract: A light diffusion module and a back light module using the same. The light diffusion module is disposed corresponding to the light source module of the back light module. The light diffusion module includes a first diffusion layer and the second diffusion layer. The first diffusion layer is disposed on top of the light source module and the top light exit surface has a plurality of first micro structures juxtapositioned to each other. The second diffusion layer is disposed on top of the first diffusion layer, and the top surface has a plurality of second micro structures juxtapositioned to each other. The ratio of the width of each first micro structure to the width of each second micro structure is between 1.1 and 1.8. The ratio of the height of each first micro structure to the height of each second micro structure is between 0.8 and 1.5.

Abstract: A semiconductor package structure includes a carrier having a plurality of leads, wherein each of the leads is composed of an inner lead and an outer lead; a chip arranged on the bottom surface of the inner leads; an electrical connecting structure and a molding component. The invention discloses that the inner leads are bent outwardly from the horizontal at top surface of the chip to form a ladder-like difference and the outer leads are extended outwardly horizontally, thus a height difference formed between the chip and the outer lead prevents the particles from contacting the chip and the outer lead at the same time to enhance the electrical reliability of the chip.

Abstract: A semiconductor packaging structure includes a plurality of first inner leads, a plurality of second inner leads, a plurality of first outer leads, a plurality of stacked chips, an encapsulating body, and a plurality of wires. Wherein, a first protrusion portion is protruded from each of the first inner leads and is formed a plurality of contact faces with height differences, a second protrusion portion is protruded from each of the second inner leads. Therefore, the wires connected to the stacked chips, the first protrusion portion of the first inner leads, and the second protrusion portion of the second inner leads can be shorten. And, the wire sweep and short-circuit can be prevented during molding process. In addition, the present invention also discloses a leadframe and manufacturing method for the leadframe and its semiconductor packaging structure.

Abstract: A semiconductor package with a substrate ID code and its manufacturing method are revealed. A circuit and a solder mask are formed on the bottom surface of a substrate where the solder mask covers most of the circuit and a circuit-free zone of the substrate. A chip is disposed on the top surface of the substrate. A substrate ID code consisting of a plurality of laser marks is inscribed in the solder mask or in a portion of an encapsulant on the bottom surface away from the circuit to show the substrate lot number on the bottom surface. Therefore, quality control and failure tracking and management can easily be implemented by tracking the substrate ID code from the semiconductor package without changing the appearance of the semiconductor package. Furthermore, the substrate ID code can be implemented by the existing laser imprinting machines for semiconductor packaging processes and be formed at the same time of formation of a product code.

Abstract: A Chip-On-Lead (COL) semiconductor package is revealed, primarily comprising a plurality of leadframe's leads each having a carrying bar, a finger and a connecting portion connecting the carrying bar to the finger. A chip has a back surface attached to the carrying bars and is electrically connected to the fingers by a plurality of bonding wires. Therein, at least one of the bonding wires overpasses one of the connecting portions without electrical relationship. An insulation tape is attached onto the connecting portions in a manner to be formed between the overpassing section of the bonding wire and the overpast connecting portion so that electrical short can be avoided during wire-bonding processes of the COL semiconductor package. Therefore, the carrying bars under the chip have more flexibility in the layout design of COL semiconductor packages to use die pad(s) with smaller dimensions or even eliminate die pad.

Abstract: A calibration method of image planar coordinate system for a high-precision image measurement system comprises: at each time an X-Y coordinate of a measurement platform is moved, rotating and finely adjusting a two-dimension coordinate system of a calibration board or a workpiece and a projection plane coordinate system of a CCD camera so as to make the both coincide with the X-Y coordinate system.

Abstract: A semiconductor package primarily comprises a plurality of leadframe's leads, a chip, a paddle, an adhesive and an encapsulant encapsulating the components mentioned above. The paddle has a carrying surface and an exposed external surface. The first chip is attached to one surface of the leads. The paddle is attached to an opposing surface of the leads by the adhesive bonding the carrying surface to the leads. Furthermore, the adhesive further encapsulates the gaps between the leads without contaminating the exposed external surface and with the exposed external surface exposed from the encapsulant. Therefore, the leads obtain a better support so that the encapsulated portions of the leads will not shift nor expose from the encapsulant during molding processes without encapsulated bubbles between the leads and the paddle. The heat dissipation is also enhanced.