Patents by Inventor Tian-Fu Chiang
Tian-Fu Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8816439Abstract: A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer.Type: GrantFiled: October 19, 2010Date of Patent: August 26, 2014Assignee: United Microelectronics Corp.Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
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Patent number: 8404535Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.Type: GrantFiled: November 25, 2011Date of Patent: March 26, 2013Assignee: United Microelectronics Corp.Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Cheng-Hsien Chou, Tian-Fu Chiang, Chien-Ming Lai, Yi-Wen Chen, Jung-Tsung Tseng, Chien-Ting Lin, Guang-Hwa Ma
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Patent number: 8193050Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.Type: GrantFiled: October 18, 2010Date of Patent: June 5, 2012Assignee: United Microelectronics Corp.Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
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Publication number: 20120064679Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.Type: ApplicationFiled: November 25, 2011Publication date: March 15, 2012Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Cheng-Hsien Chou, Tian-Fu Chiang, Chien-Ming Lai, Yi-Wen Chen, Jung-Tsung Tseng, Chien-Ting Lin, Guang-Hwa Ma
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Patent number: 8084824Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.Type: GrantFiled: September 11, 2008Date of Patent: December 27, 2011Assignee: United Microelectronics Corp.Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Cheng-Hsien Chou, Tian-Fu Chiang, Chien-Ming Lai, Yi-Wen Chen, Jung-Tsung Tseng, Chien-Ting Lin, Guang-Hwa Ma
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Patent number: 7998818Abstract: A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.Type: GrantFiled: August 25, 2010Date of Patent: August 16, 2011Assignee: United Microelectronics Corp.Inventors: Tian-Fu Chiang, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
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Patent number: 7932146Abstract: A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resistor region of the substrate. Next, a portion of the polysilicon layer disposed in the resistor is removed, and the remaining polysilicon layer is patterned to create a step height between the surface of the polysilicon layer disposed in the transistor region and the surface of the polysilicon layer disposed in the resistor region.Type: GrantFiled: March 20, 2008Date of Patent: April 26, 2011Assignee: United Microelectronics Corp.Inventors: Yi-Wen Chen, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Tian-Fu Chiang, Chien-Ting Lin, Guang-Hwa Ma
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Patent number: 7888195Abstract: A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region.Type: GrantFiled: August 26, 2008Date of Patent: February 15, 2011Assignee: United Microelectronics Corp.Inventors: Chien-Ting Lin, Li-Wei Cheng, Jung-Tsung Tseng, Che-Hua Hsu, Chih-Hao Yu, Tian-Fu Chiang, Yi-Wen Chen, Chien-Ming Lai, Cheng-Hsien Chou
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Publication number: 20110034019Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.Type: ApplicationFiled: October 18, 2010Publication date: February 10, 2011Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
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Publication number: 20110031558Abstract: A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer.Type: ApplicationFiled: October 19, 2010Publication date: February 10, 2011Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
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Publication number: 20110018072Abstract: A metal gate transistor is disclosed. The metal gate transistor preferably includes: a substrate, a metal gate disposed on the substrate, and a source/drain region disposed in the substrate with respect to two sides of the metal gate. The metal gate includes a U-shaped high-k dielectric layer, a U-shaped cap layer disposed over the surface of the U-shaped high-k dielectric layer, and a U-shaped metal layer disposed over the U-shaped cap layer.Type: ApplicationFiled: September 29, 2010Publication date: January 27, 2011Inventors: Chien-Ting Lin, Li-Wei Cheng, Jung-Tsung Tseng, Che-Hua Hsu, Chih-Hao Yu, Tian-Fu Chiang, Yi-Wen Chen, Chien-Ming Lai, Cheng-Hsien Chou
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Publication number: 20100317182Abstract: A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.Type: ApplicationFiled: August 25, 2010Publication date: December 16, 2010Inventors: Tian-Fu Chiang, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
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Patent number: 7838946Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.Type: GrantFiled: March 28, 2008Date of Patent: November 23, 2010Assignee: United Microelectronics Corp.Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
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Patent number: 7804141Abstract: A semiconductor element structure includes a first MOS having a first high-K material and a first metal for use in a first gate, a second MOS having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connecting the first gate and the second gate for electrically connecting the first gate and the second gate, wherein the bridge channel is embedded in at least one of the first gate and the second gate.Type: GrantFiled: February 19, 2008Date of Patent: September 28, 2010Assignee: United Microelectronics Corp.Inventors: Tian-Fu Chiang, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
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Patent number: 7799630Abstract: A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate.Type: GrantFiled: January 23, 2008Date of Patent: September 21, 2010Assignee: United Microelectronics Corp.Inventors: Chih-Hao Yu, Li-Wei Cheng, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ting Lin, Che-Hua Hsu, Guang-Hwa Ma
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Publication number: 20100059833Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.Type: ApplicationFiled: September 11, 2008Publication date: March 11, 2010Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Cheng-Hsien Chou, Tian-Fu Chiang, Chien-Ming Lai, Yi-Wen Chen, Jung-Tsung Tseng, Chien-Ting Lin, Guang-Hwa Ma
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Publication number: 20100052074Abstract: A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region.Type: ApplicationFiled: August 26, 2008Publication date: March 4, 2010Inventors: Chien-Ting Lin, Li-Wei Cheng, Jung-Tsung Tseng, Che-Hua Hsu, Chih-Hao Yu, Tian-Fu Chiang, Yi-Wen Chen, Chien-Ming Lai, Cheng-Hsien Chou
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Publication number: 20090242997Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.Type: ApplicationFiled: March 28, 2008Publication date: October 1, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
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Publication number: 20090236669Abstract: A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resistor region of the substrate. Next, a portion of the polysilicon layer disposed in the resistor is removed, and the remaining polysilicon layer is patterned to create a step height between the surface of the polysilicon layer disposed in the transistor region and the surface of the polysilicon layer disposed in the resistor region.Type: ApplicationFiled: March 20, 2008Publication date: September 24, 2009Inventors: Yi-Wen Chen, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Tian-Fu Chiang, Chien-Ting Lin, Guang-Hwa Ma
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Publication number: 20090206415Abstract: A semiconductor element structure includes a first MOS having a first high-K material and a first metal for use in a first gate, a second MOS having a second high-K material and a second metal for use in a second gate and a bridge channel disposed in a recess connecting the first gate and the second gate for electrically connecting the first gate and the second gate, wherein the bridge channel is embedded in at least one of the first gate and the second gate.Type: ApplicationFiled: February 19, 2008Publication date: August 20, 2009Inventors: Tian-Fu Chiang, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma