Abstract: This application provides an adhesive composition. The adhesive composition includes an adhesive matrix and a modified polymer. A main chain of the modified polymer includes a boron-oxygen coordinate bond and/or a bridging boron-oxygen coordinate bond. A terminal group or a side chain of the modified polymer or both include at least one of a hydroxyl group, an acrylate group, and a vinyl group. This application further provides a preparation method of the adhesive composition, an optical adhesive film, a foldable screen using the optical adhesive film, and an electronic device using the optical adhesive film or the foldable screen.

Abstract: The present disclosure provides a method and apparatus for determining a utilization rate of wireless resources, an electronic device and a storage medium. The method includes acquiring communication data within a statistical period of a cell; determining a channel non-space division occupied wireless resource within in the statistical period; determining a channel space division occupied wireless resource within the statistical period; determining a channel available wireless resource within the statistical period; and determining the utilization rate of wireless resources.

Abstract: The present disclosure relates to display apparatuses and methods for manufacturing the display apparatuses. One example display apparatus includes an array substrate and a laminated structure. The array substrate includes a substrate and an array layer located on a side of the substrate. The laminated structure is located on a side that is of the array layer and that is opposite to the substrate, and includes a first film layer and a second film layer. The first film layer is located on a side that is of the second film layer and that is opposite to the substrate, and is formed by a high modulus material. An elastic modulus of the high modulus material is E1, and 50 Mpa?E1?5 Gpa. The second film layer is formed by a modified energy absorption impact resistance material has viscosity and shear thickening behavior.

Abstract: The disclosure provides a power semiconductor device and manufacturing method thereof. A plurality of second resistive field plate structures extending through an epitaxial layer in a first direction into a substrate are arranged in a termination region of the epitaxial layer and the plurality of second resistive field plate structures are arranged radially in a first plane. A plurality of tightly coupled second resistive field plates extending from a side close to a cell region to a side far away from the cell region form a more uniform three-dimensional electric field distribution diverging around the cell region, which optimizes a guiding and binding effect on a charge in a space depletion region of the cell region and improves a withstand voltage performance of the whole power semiconductor device.

Abstract: A protective coating layer, an electronic device including such a protective coating layer, and the methods of making the same are provided. The electronic device includes a substrate, a thin film circuit layer disposed over the substrate, and a protective coating layer disposed over the thin film circuit layer. The protective coating layer includes a first coating and a second coating disposed over the first coating. Each coating has a cross-plane thermal conductivity in a direction normal to a respective coating surface equal to or higher than 0.5 W/(m*K). The first coating and the second coating have different crystal or amorphous structures, different crystalline orientations, different compositions, or a combination thereof to provide different nanoindentation hardness. The first coating has a hardness lower than that of the second coating.

Abstract: The MOS device with resistive field plate for realizing conductance modulation field effect in the present invention is based on the existing trench gate MOS device, and a semi-insulating resistive field plate electrically connected to the trench gate structure and the drain structure is added in the drift region, where the trench gate structure can control the on-off of the MOS channel, and the semi-insulating resistive field plate can adjust the doping concentration of the drift region to modulate the conductance of the on-state drift region and the distribution of off-state high-voltage blocking electric field, thus a lower on-resistance can be obtained. In addition, the modern 2.5-dimensional processing technology based on deep trench etching is adopted in the present invention, which is conducive to the miniaturization design and high density design of the structure and is more suitable for the More than Moore (beyond Moore) development of modern integrated semiconductor devices.

Abstract: A multi-segment pixel matrix, a sensor or device, a system, and a method, for biometric sensing, are provided. Such a device or system includes a sensor comprising a pixel matrix having two or more pixel arrays as separate segments logically divided in the pixel matrix. The pixel matrix may include both thermal sensing pixels and capacitive sensing nodes. The device or system may include a plurality of application-specific intergrade circuits (ASICs) coupled to the sensor. Each ASIC is configured to capture image data of a biometric pattern measured by at least one pixel array. Each pixel array is independently driven and scanned by one or more of the plurality of the ASICs. The device or system further includes a microcontroller unit coupled to the plurality of ASICs and are used to process the image data and/or control operation of the system. Such a sensor can be a fingerprint sensor.

Abstract: A shared-dielectric MOSFET device with a resistive-field-plate and a preparation method are provided. In the shared-dielectric MOSFET device, the semi-insulating resistive-field-plate electrically connected to the trench gate structure and the drain structure is introduced in the drift region of the existing trench gate MOS devices, and when the trench gate structure controls the MOS channel to be turned on or turned off, the semi-insulating resistive-field-plate can adjust the doping concentration of the drift region, to modulate the conductance of the on-state drift region and the distribution of a off-state high-voltage blocking electric field, thereby obtaining a lower on-resistance. Meanwhile, in the preparation method of the present disclosure, the modern 2.

Abstract: A multi-segment pixel matrix, a sensor or device, a system, and a method, for biometric sensing, are provided. Such a device or system includes a sensor comprising a pixel matrix having two or more pixel arrays as separate segments logically divided in the pixel matrix. The pixel matrix may include both thermal sensing pixels and capacitive sensing nodes. The device or system may include a plurality of application-specific intergrade circuits (ASICs) coupled to the sensor. Each ASIC is configured to capture image data of a biometric pattern measured by at least one pixel array. Each pixel array is independently driven and scanned by one or more of the plurality of the ASICs. The device or system further includes a microcontroller unit coupled to the plurality of ASICs and are used to process the image data and/or control operation of the system. Such a sensor can be a fingerprint sensor.

Abstract: Systems and methods for manufacturing flexible electronics are described herein. Methods in accordance with embodiments of the present technology can include disposing electrical features, such as thin film circuits, on a first side of a glass substrate, applying a first protective material over the electronic features, and exposing a second side of the glass substrate to a chemical etching tank to thin the glass substrate to a predetermined thickness. The thinning process can remove cracks and other defects from the second side of the glass substrate and enhance the flexibility of the electronic assembly. A second protective material can be disposed on the second side of the thinned glass substrate to maintain the enhanced backside surface of the glass substrate. In some embodiments, the method also includes singulating the plurality of electronic features into individual electronic components by submerging the electronic assembly into a chemical etching tank.

Abstract: A multi-segment pixel matrix, a sensor or device, a system, and a method, for biometric sensing, are provided. Such a device or system includes a sensor comprising a pixel matrix having two or more pixel arrays as separate segments logically divided in the pixel matrix. The pixel matrix may include both thermal sensing pixels and capacitive sensing nodes. The device or system may include a plurality of application-specific intergrade circuits (ASICs) coupled to the sensor. Each ASIC is configured to capture image data of a biometric pattern measured by at least one pixel array. Each pixel array is independently driven and scanned by one or more of the plurality of the ASICs. The device or system further includes a microcontroller unit coupled to the plurality of ASICs and are used to process the image data and/or control operation of the system. Such a sensor can be a fingerprint sensor.

Abstract: Systems and methods for manufacturing flexible electronics are described herein. Methods in accordance with embodiments of the present technology can include disposing electrical features, such as thin film circuits, on a first side of a glass substrate, applying a first protective material over the electronic features, and exposing a second side of the glass substrate to a chemical etching tank to thin the glass substrate to a predetermined thickness. The thinning process can remove cracks and other defects from the second side of the glass substrate and enhance the flexibility of the electronic assembly. A second protective material can be disposed on the second side of the thinned glass substrate to maintain the enhanced backside surface of the glass substrate. In some embodiments, the method also includes singulating the plurality of electronic features into individual electronic components by submerging the electronic assembly into a chemical etching tank.

Abstract: Systems and methods for manufacturing flexible electronics are described herein. Methods in accordance with embodiments of the present technology can include disposing electrical features, such as thin film circuits, on a first side of a glass substrate, applying a first protective material over the electronic features, and exposing a second side of the glass substrate to a chemical etching tank to thin the glass substrate to a predetermined thickness. The thinning process can remove cracks and other defects from the second side of the glass substrate and enhance the flexibility of the electronic assembly. A second protective material can be disposed on the second side of the thinned glass substrate to maintain the enhanced backside surface of the glass substrate. In some embodiments, the method also includes singulating the plurality of electronic features into individual electronic components by submerging the electronic assembly into a chemical etching tank.

Abstract: A protective coating layer, an electronic device including such a protective coating layer, and the methods of making the same are provided. The electronic device includes a substrate, a thin film circuit layer disposed over the substrate, and a protective coating layer disposed over the thin film circuit layer. The protective coating layer includes a first coating and a second coating disposed over the first coating. Each coating has a cross-plane thermal conductivity in a direction normal to a respective coating surface equal to or higher than 0.5 W/(m*K). The first coating and the second coating have different crystal or amorphous structures, different crystalline orientations, different compositions, or a combination thereof to provide different nanoindentation hardness. The first coating has a hardness lower than that of the second coating.

Abstract: A protective coating layer, an electronic device including such a protective coating layer, and the methods of making the same are provided. The electronic device includes a substrate, a thin film circuit layer disposed over the substrate, and a protective coating layer disposed over the thin film circuit layer. The protective coating layer includes a first coating and a second coating disposed over the first coating. Each coating has a cross-plane thermal conductivity in a direction normal to a respective coating surface equal to or higher than 0.5 W/(m*K). The first coating and the second coating have different crystal structures, or different crystalline orientations, or different compositions, or a combination thereof to provide different nanoindentation hardness. The first coating has a hardness lower than that of the second coating.

Abstract: Systems and methods for manufacturing flexible electronics are described herein. Methods in accordance with embodiments of the present technology can include disposing electrical features, such as thin film circuits, on a first side of a glass substrate, applying a first protective material over the electronic features, and exposing a second side of the glass substrate to a chemical etching tank to thin the glass substrate to a predetermined thickness. The thinning process can remove cracks and other defects from the second side of the glass substrate and enhance the flexibility of the electronic assembly. A second protective material can be disposed on the second side of the thinned glass substrate to maintain the enhanced backside surface of the glass substrate. In some embodiments, the method also includes singulating the plurality of electronic features into individual electronic components by submerging the electronic assembly into a chemical etching tank.

Abstract: A protective coating layer, an electronic device including such a protective coating layer, and the methods of making the same are provided. The electronic device includes a substrate, a thin film circuit layer disposed over the substrate, and a protective coating layer disposed over the thin film circuit layer. The protective coating layer includes a first coating and a second coating disposed over the first coating. Each coating has a cross-plane thermal conductivity in a direction normal to a respective coating surface equal to or higher than 0.5 W/(m*K). The first coating and the second coating have different crystal structures, or different crystalline orientations, or different compositions, or a combination thereof to provide different nanoindentation hardness. The first coating has a hardness lower than that of the second coating.

Abstract: A method of fabricating a high mobility semiconductor metal oxide thin film transistor including the steps of depositing a layer of semiconductor metal oxide material, depositing a blanket layer of etch-stop material on the layer of MO material, and patterning a layer of source/drain metal on the blanket layer of etch-stop material including etching the layer of source/drain metal into source/drain terminals positioned to define a channel area in the semiconductor metal oxide layer. The etch-stop material being electrically conductive in a direction perpendicular to the plane of the blanket layer at least under the source/drain terminals to provide electrical contact between each of the source/drain terminals and the layer of semiconductor metal oxide material. The etch-stop material is also chemical robust to protect the layer of semiconductor metal oxide channel material during the etching process.

Abstract: A thin film circuit includes a thin film transistor with a metal oxide semiconductor channel having a conduction band minimum (CBM) with a first energy level. The transistor further includes a layer of passivation material covering at least a portion of the metal oxide semiconductor channel. The passivation material has a conduction band minimum (CBM) with a second energy level. The second energy level being lower than, equal to, or no more than 0.5 eV above the first energy level. The circuit is used for an electronic device including any one of an AMLCD, AMOLED, AMLED, AMEPD.

Abstract: A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level. Providing additional passivation layer(s) on top of the transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment.