Patents by Inventor Tianchun Ye

Tianchun Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12197282
    Abstract: A data recovery method for a flash memory includes: reading data from the flash memory by using preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step size according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, and repeating the operation of calculating a check node error rate corresponding to the data to operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, until the check node error rate is minimum; and selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory, so as to perform data recovery.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: January 14, 2025
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Qianhui Li, Qi Wang, Liu Yang, Yiyang Jiang, Xiaolei Yu, Jing He, Zongliang Huo, Tianchun Ye
  • Publication number: 20240421032
    Abstract: The memory cell includes: an array of channel layers including N channel layers vertically provided on a substrate, a tunneling layer and a memory layer being sequentially provided on an outer side of the channel layers; N thermal conductive cores provided in the N channel layers respectively and penetrating the substrate; and an array of thermocouples including a thermocouple word line layer grown on the substrate and N thermocouple layers on the thermocouple word line layer, the thermocouple layers being connected one-to-one with the thermal conductive cores. A first potential difference is applied between the thermocouple word line layer and the thermocouple layer, and the thermal conductive core connected with the thermocouple layer is heated, so that the channel layer and the memory layer corresponding to the thermal conductive core are maintained at first and second preset temperatures respectively under a thermal insulation effect of the tunneling layer.
    Type: Application
    Filed: November 2, 2021
    Publication date: December 19, 2024
    Inventors: Gang ZHANG, Chunlong LI, Zongliang HUO, Tianchun YE
  • Publication number: 20240365534
    Abstract: A memory device, including: device layers vertically stacked on a substrate, each device layer including an array of active regions of selection transistors, the array including rows in a first direction and columns in a second direction, the active region including a lower source/drain region, a channel portion, and an upper source/drain region; bit lines arranged in the second direction and extending in the first direction along rows; word line layers vertically stacked and corresponding to the device layers, and each including word lines arranged in the first direction and extending in the second direction to at least partially surround a channel portion in a column of a device layer; sub bit lines extending vertically from each bit line and each electrically connected to a lower source/drain region in a row in each device layer above the bit line; and a memory element electrically connected to the upper source/drain region.
    Type: Application
    Filed: April 9, 2024
    Publication date: October 31, 2024
    Inventors: Huilong ZHU, Tianchun YE, Jun LUO
  • Patent number: 12088323
    Abstract: A read-write method includes: sequentially writing, in a first direction, a code word obtained by information-bit encoding into a target memory cell in each layer of memory cell array in the three-dimensional memory; randomly reading the target memory cell in each layer of memory cell array, or sequentially reading the target memory cell in each layer of memory cell array in a second direction; and determining an LLR value of a current target memory cell according to a storage time corresponding to the current target memory cell when reading, a threshold voltage partition corresponding to the current target memory cell when reading, a comprehensive distribution state corresponding to the current target memory cell when reading, and a pre-established LLR table, so as to perform a soft decoding operation on the code word in the current target memory cell based on the LLR value of the current target memory cell.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: September 10, 2024
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Qi Wang, Yiyang Jiang, Qianhui Li, Zongliang Huo, Tianchun Ye
  • Publication number: 20240220355
    Abstract: A data recovery method for a flash memory includes: reading data from the flash memory by using preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step size according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, and repeating the operation of calculating a check node error rate corresponding to the data to operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, until the check node error rate is minimum; and selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory, so as to perform data recovery.
    Type: Application
    Filed: April 8, 2021
    Publication date: July 4, 2024
    Inventors: Qianhui LI, Qi WANG, Liu YANG, Yiyang JIANG, Xiaolei YU, Jing HE, Zongliang HUO, Tianchun YE
  • Patent number: 11929304
    Abstract: A semiconductor apparatus with a heat dissipation conduit in a sidewall interconnection structure, a method of manufacturing the semiconductor apparatus, and an electronic device including the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes: a carrier substrate having a first region and a second region adjacent to each other; a semiconductor device on the first region; and an interconnection structure on the second region, wherein the interconnection structure includes: an electrical isolation layer; a conductive structure in the electrical isolation layer, wherein at least a part of components require to be electrically connected in the semiconductor device is in contact with and therefore electrically connected to the conductive structure in a lateral direction, wherein the conductive structure is located at a corresponding height in the interconnection structure; and a heat dissipation conduit in the electrical isolation layer.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: March 12, 2024
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Tianchun Ye
  • Publication number: 20240038318
    Abstract: A read-write method includes: sequentially writing, in a first direction, a code word obtained by information-bit encoding into a target memory cell in each layer of memory cell array in the three-dimensional memory; randomly reading the target memory cell in each layer of memory cell array, or sequentially reading the target memory cell in each layer of memory cell array in a second direction; and determining an LLR value of a current target memory cell according to a storage time corresponding to the current target memory cell when reading, a threshold voltage partition corresponding to the current target memory cell when reading, a comprehensive distribution state corresponding to the current target memory cell when reading, and a pre-established LLR table, so as to perform a soft decoding operation on the code word in the current target memory cell based on the LLR value of the current target memory cell.
    Type: Application
    Filed: November 25, 2020
    Publication date: February 1, 2024
    Inventors: Qi Wang, Yiyang Jiang, Qianhui Li, Zongliang Huo, Tianchun Ye
  • Patent number: 11839085
    Abstract: Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: December 5, 2023
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Zhaozhao Hou, Tianchun Ye, Chaolei Li
  • Patent number: 11594608
    Abstract: A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 28, 2023
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Jiaxin Yao, Qingzhu Zhang, Zhaohao Zhang, Tianchun Ye
  • Publication number: 20220254702
    Abstract: A semiconductor apparatus with a heat dissipation conduit in a sidewall interconnection structure, a method of manufacturing the semiconductor apparatus, and an electronic device including the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes: a carrier substrate having a first region and a second region adjacent to each other; a semiconductor device on the first region; and an interconnection structure on the second region, wherein the interconnection structure includes: an electrical isolation layer; a conductive structure in the electrical isolation layer, wherein at least a part of components require to be electrically connected in the semiconductor device is in contact with and therefore electrically connected to the conductive structure in a lateral direction, wherein the conductive structure is located at a corresponding height in the interconnection structure; and a heat dissipation conduit in the electrical isolation layer.
    Type: Application
    Filed: February 8, 2022
    Publication date: August 11, 2022
    Inventors: Huilong ZHU, Tianchun YE
  • Patent number: 11411091
    Abstract: A method for manufacturing a stacked gate-all-around nano-sheet CMOS device, including: providing a substrate with a fin structure, where a channel layer for an NMOS is a sacrificial layer for a PMOS, a channel layer for the PMOS is a sacrificial layer for the NMOS; and mobility of holes in the second material is greater than mobility of holes in the first material; forming a dummy gate stack extending across the fin structure; forming source-or-drain regions in the fin structure at two sides of the dummy gate stack; removing the dummy gate stack and the sacrificial layers covered by the dummy gate stack, to expose a surface of a part of the channel layer that is located between the source-or-drain regions, where a nano-sheet array is formed by the channel layer with the exposed surface; and forming a gate stack structure surrounding each nano sheet in the nano-sheet array.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 9, 2022
    Inventors: Huaxiang Yin, Tianchun Ye, Qingzhu Zhang, Jiaxin Yao
  • Publication number: 20220231144
    Abstract: A semiconductor structure, a method for manufacturing the semiconductor structure, and a transistor. A doped structure is provided, where the doped structure includes a dopant. A surface of the doped structure is oxidized to form the oxide film. In such case, the dopant at an interface between the oxide film and the doped structure may be redistributed, and thereby a segregated-dopant layer is formed inside or at a surface of the doped structure under the oxide film. A concentration of the dopant is higher in the segregated-dopant layer than in other regions of the doped structure. After the oxide film is removed, the doped structure with a high surface doping concentration can be obtained without an additional doping process. Therefore, after a conducting structure is formed on the segregated-dopant layer, a low contact resistance between the conducting structure and the doped structure is obtained, and a device performance is improved.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 21, 2022
    Inventors: Jun LUO, Tianchun YE, Dan ZHANG
  • Publication number: 20220115513
    Abstract: A method for manufacturing a stacked gate-all-around nano-sheet CMOS device, including: providing a substrate with a fin structure, where a channel layer for an NMOS is a sacrificial layer for a PMOS, a channel layer for the PMOS is a sacrificial layer for the NMOS; and mobility of holes in the second material is greater than mobility of holes in the first material; forming a dummy gate stack extending across the fin structure; forming source-or-drain regions in the fin structure at two sides of the dummy gate stack; removing the dummy gate stack and the sacrificial layers covered by the dummy gate stack, to expose a surface of a part of the channel layer that is located between the source-or-drain regions, where a nano-sheet array is formed by the channel layer with the exposed surface; and forming a gate stack structure surrounding each nano sheet in the nano-sheet array.
    Type: Application
    Filed: October 30, 2019
    Publication date: April 14, 2022
    Inventors: Huaxiang YIN, Tianchun YE, Qingzhu ZHANG, Jiaxin YAO
  • Publication number: 20220085070
    Abstract: Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.
    Type: Application
    Filed: November 4, 2019
    Publication date: March 17, 2022
    Inventors: Huaxiang YIN, Zhaozhao HOU, Tianchun YE, Chaolei LI
  • Patent number: 11069808
    Abstract: A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1?x?0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 20, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Qingzhu Zhang, Zhaohao Zhang, Tianchun Ye
  • Patent number: 11056580
    Abstract: A semiconductor device comprise a substrate, source/drain regions, a channel region, a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer comprises a barrier layer, a storage layer, a first interface layer, a tunneling layer, a second interface layer. In accordance with the semiconductor device and the manufacturing method of the present invention, an interface layer is added between the storage layer and tunneling layer in the gate dielectric by adjusting process step, and the peak concentration and peak location of nitrogen can be flexibly adjusted, effectively improving the quality of the interface between the storage layer and the tunneling layer in the gate dielectric layer, increasing process flexibility, improving device reliability and current characteristics.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: July 6, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Tianchun Ye
  • Patent number: 10991877
    Abstract: A multi-state memory and a method for manufacturing the same. A magnetoresistive tunnel junction is disposed on a spin-orbit coupling layer, and thermal annealing is performed after dopant ions are injected from a side of the magnetoresistive tunnel junction. The concentration of dopant ions in the magnetoresistive tunnel junction has a gradient variation along the direction that is perpendicular to the direction of the current and within the plane in which the spin-orbit coupling layer is located. Symmetry along the direction perpendicular to the direction of the current is broken. In a case a current flows into the spin-orbit coupling layer, resistance are outputted in multiple states in linearity with the current. The multi-state storage is achieved. It can meet a requirement on hardware of neural network synapses, and is applicable to calculation in a neural network.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: April 27, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Meiyin Yang, Jun Luo, Sumei Wang, Jing Xu, Yanru Li, Junfeng Li, Yan Cui, Wenwu Wang, Tianchun Ye
  • Publication number: 20200335596
    Abstract: A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.
    Type: Application
    Filed: September 5, 2019
    Publication date: October 22, 2020
    Inventors: Huaxiang YIN, Jiaxin YAO, Qingzhu ZHANG, Zhaohao ZHANG, Tianchun YE
  • Publication number: 20200328309
    Abstract: A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1?x?0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.
    Type: Application
    Filed: December 19, 2019
    Publication date: October 15, 2020
    Inventors: Huaxiang YIN, Qingzhu ZHANG, Zhaohao ZHANG, Tianchun YE
  • Publication number: 20200303635
    Abstract: A multi-state memory and a method for manufacturing the same. A magnetoresistive tunnel junction is disposed on a spin-orbit coupling layer, and thermal annealing is performed after dopant ions are injected from a side of the magnetoresistive tunnel junction. The concentration of dopant ions in the magnetoresistive tunnel junction has a gradient variation along the direction that is perpendicular to the direction of the current and within the plane in which the spin-orbit coupling layer is located. Symmetry along the direction perpendicular to the direction of the current is broken. In a case a current flows into the spin-orbit coupling layer, resistance are outputted in multiple states in linearity with the current. The multi-state storage is achieved. It can meet a requirement on hardware of neural network synapses, and is applicable to calculation in a neural network.
    Type: Application
    Filed: September 4, 2019
    Publication date: September 24, 2020
    Inventors: Meiyin YANG, Jun Luo, Sumei Wang, Jing Xu, Yanru Li, Junfeng Li, Yan Cui, Wenwu Wang, Tianchun Ye