Abstract: A three-dimensional memory device and method of manufacturing the same, an isolation structure is embedded between the common source region and the substrate thereunder, which can inhibit the undesired diffusion of impurities during the implantation of the common source region, avoiding operation failure due to excessive diffusion of impurities. In programming and reading states of the three-dimensional memory device, electrons flow from the common source region to bit line; while in erase states, holes are injected from the substrate. Due to the isolation structure, the three-dimensional memory device achieves spatial separation of electrons from holes required for programming/erasing, improving the erasing efficiency and the integration as well.

Abstract: A semiconductor device comprise a substrate, source/drain regions, a channel region, a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer comprises a barrier layer, a storage layer, a first interface layer, a tunneling layer, a second interface layer. In accordance with the semiconductor device and the manufacturing method of the present invention, an interface layer is added between the storage layer and tunneling layer in the gate dielectric by adjusting process step, and the peak concentration and peak location of nitrogen can be flexibly adjusted, effectively improving the quality of the interface between the storage layer and the tunneling layer in the gate dielectric layer, increasing process flexibility, improving device reliability and current characteristics.

Abstract: A method of manufacturing a semiconductor device, comprising the steps of: forming a gate dielectric layer and a first amorphous channel layer on a substrate; thinning the first amorphous channel layer; etching the first amorphous channel layer and the gate dielectric layer until the substrate is exposed; forming a second amorphous channel layer on the first amorphous channel layer and the substrate; annealing such that the first amorphous channel layer and the second amorphous channel layer are converted into a polycrystalline channel layer; and thinning the polycrystalline channel layer. According to the method of manufacturing semiconductor device of the present invention, the grain size of the polycrystalline thin film is increased by depositing a thick amorphous film and then annealing and thinning it.

Abstract: One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.

Abstract: Provided is a method for manufacturing a p-type MOSFET, including: forming a part of the MOSFET on a semiconductor substrate including source/drain regions, a replacement gate, and a gate spacer; removing the replacement gate stack of the MOSFET to form a gate opening; forming an interface oxide layer on the exposed surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interface oxide layer; forming a first metal gate layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.

Abstract: One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.

Abstract: A method for improving anti-radiation performance of SOI structure that includes implementing particle implantations of high-energy neutrons, protons and ?-rays to a buried oxide layer of an SOI structure, and then performing annealing process. The high-energy particle implantation introduces displacement damage to the buried oxide layer of the SOI structure.

Abstract: The present invention provides a method for improving anti-radiation performance of SOI structure comprising following steps: implementing particle implantations of high-energy neutrons, protons and ?-rays to an SOI structure, and then performing annealing process. The present invention aims to improving anti-radiation performance of SOI devices by means of introducing displacement damage into a buried oxide layer through implantation of high-energy particles.

Abstract: An embodiment of the invention discloses a graphene device comprising a plurality of graphene channels and a gate, wherein one end of all the graphene channels is connected to one terminal, all the graphene channels are in contact with and electrically connected with the gate, and the angles between the graphene channels and the gate are mutually different. Due to a different incident wave angle for a different graphene channel, each of the graphene channels has a different tunneling probability, each of the graphene channels has a different conduction condition, and the graphene device may be used as a device such as a multiplexer or a demultiplexer, etc.