Abstract: The present disclosure provides a method for experimentally determining a critical sand-carrying gas velocity of a shale gas well. The method includes: collecting well structure and production data, calculating parameter ranges of a gas flow velocity and a liquid flow velocity; carrying out a physical simulation experiment of sand carrying in the shale gas well to obtain the sand holding capacity of the wellbore under different experimental conditions, and calculating a sand holding rate; by observing a change curve of the sand holding rate of the wellbore vs. the gas flow velocity, defining a turning point, and sensitively analyzing the influence of other experimental variables on the turning point, to calculate the critical sand-carrying production of the shale gas well under different conditions. Therefore, this calculation method is simple and applicable, and provides a theoretical basis for the optimization design of water drainage and gas production process.

Abstract: Disclosed are a model parameter training method and a terminal based on federation learning, and a medium. The method includes: determining a feature intersection of a first sample of the first terminal and a second sample of a second terminal, training the first sample based on the feature intersection to obtain a first mapping model, sending the first mapping model to the second terminal; receiving a second encryption mapping model sent by the second terminal, predicting a missing feature of the first sample of the first terminal according to the second encryption mapping model to obtain a first encryption supplementary sample; receiving a first encryption federation learning model parameter sent by a third terminal, training a federation learning model to be trained according to the first encryption federation learning model parameter, and calculating a first encryption loss value; and sending the first encryption loss value to the third terminal.

Abstract: A die bonding method includes temporarily bonding a first carrier wafer to a front side of a device wafer, so that a back-side connection structure can be formed on a back side of the device wafer to lead out an interconnect structure in the device wafer to the back side of the device wafer. Moreover, through bonding a second carrier wafer to the back side of the device wafer, the first carrier wafer can be debonded. After the device wafer and the second carrier wafer are debonded, a second bonding adhesive is retained in order to provide protection to the back side of the device wafer during the subsequent dicing of the device wafer and to avoid particles or etching by-products produced during the dicing process from adhering to the back side of the device wafer.

Abstract: A die-to-wafer stacking method includes: providing a wafer to be processed, including a substrate, a dielectric layer on the substrate and a metal layer embedded in the dielectric layer; forming a bonding layer covering the dielectric layer; picking up dies to be bonded from the wafer to be processed and arranging the dies to be bonded on an electrostatic chuck; and bonding the dies arranged on the electrostatic chuck, as a whole, to a wafer to be bonded. Pre-arranging all the dies to be bonded on the electrostatic chuck and then bonding the dies on the electrostatic chuck, as a whole, to the wafer to be bonded can greatly shorten post-activation waiting times of dies before they are bonded to the wafer and thus reduce the risk of loss of activation.

Abstract: A method of bonding first die(s) to a wafer and a die-stack structure includes: providing a first layer of first die(s), each of the first die(s) including a first metal layer; providing the wafer, which includes a second metal layer; bonding the first die(s) to the wafer; forming an insulating layer and a hole, the insulating layer covering the wafer around the first die(s) or filling gap(s) between the first die(s), the hole formed in the insulating layer around the first die(s); forming an interconnect structure in the hole, the first metal layer, the second metal layer and the interconnect structure are electrically connected, thus establishing electrical connection between the first die(s) and the wafer. In this method, it is unnecessary to form TSV within the first die(s), reducing difficulties in the design of internal wiring within the first die(s) and resulting in area savings of the first die(s).

Abstract: A first opening is formed in a first metal layer by etching away part of the first metal layer, and a second metal layer is filled in the first opening and is electrically connected to the remainder of the first metal layer. A TSV extends sequentially through a substrate and a partial thickness of a dielectric layer so that the second metal layer is exposed therein, and an interconnect layer in the TSV is electrically connected to the second metal layer. Therefore, the first metal layer can be picked up as long as projections of the second metal layer and the interconnect layer are encompassed within a projection of the first metal layer on the substrate, without any additional lateral area of the first metal layer being occupied by the TSV. The second metal layer that leads out the first metal layer can be formed by only one photolithography process.

Abstract: A backside illuminated (BSI) image sensor substrate and a method of manufacturing a BSI image sensor are disclosed. A first nitride layer (9) is formed on a metal material layer (70), and a first dry etching process is then performed on both the first nitride layer (9) and the metal material layer (70). In this way, during the etching of the metal material layer (70), the first nitride layer (9) is bombarded so that nitrogen atoms or nitrogen ions escape from the first nitride layer (9), during the formation of a metal grid layer (7), the escaping nitrogen atoms or nitrogen ions react with the metal on sidewalls of second openings (7a), forming a metal nitride layer which protects the metal grid at the sidewalls of the second openings (7a) from being damaged. As such, the resulting metal grid layer (7) has smooth sidewalls and good morphology.

Abstract: A method of manufacturing a semiconductor device includes: providing bonded first and second wafers; forming a patterned insulating layer on the second substrate, the patterned insulating layer having first holes and dummy holes both exposing the second substrate; forming a protective layer, which fills a partial depth of the dummy holes and covers side surfaces of the first holes; forming through-silicon vias (TSVs); and forming a second metal layer including an interconnect metal layer and a dummy metal layer, the interconnect metal layer filling the TSVs and electrically connected to the first metal layer, the dummy metal layer filling the dummy holes. The formation of the dummy metal layer is integrated in the TSV process and is therefore done without using any additional process or adding additional cost to enable uniform pattern density (e.g., metal density) across the surface of the second wafer and enhanced CMP uniformity.

Abstract: A die bonding method is disclosed, through coating bonding adhesive on front side of device wafer and bonding carrier wafer thereto, back-side connection structure can be formed on back side of device wafer to lead out an interconnect structure in device wafer to back side of device wafer, and dies thereon can be bonded at front sides to target wafer. Moreover, after device wafer is debonded from carrier wafer, the bonding adhesive is retained on front side of device wafer to provide protection to front side of device wafer during subsequent dicing of device wafer, and to avoid particles or etching by-products produced during dicing process from adhering to front side of device wafer. Such etching by-products are subsequently removed along with the bonding adhesive, ensuring cleanness of front sides of individual dies resulting from dicing process and improved quality of bonding of dies at front sides to target wafer.

Abstract: A method of design for matching of wafers, a wafer bonding structure and a chip bonding structure includes: providing a first wafer including unit arrays that each include at least two first dies; providing a second wafer including second dies that each cover at least one of the unit arrays, and the second dies matched in terms of performance with the first dies in the unit arrays that it covers. The first and second wafers are provided with corresponding alignment marks. With this application, two or more wafers with corresponding dies differing considerably in terms of shape or area can be designed to match each other and become suitable to be bonded together. This enables effective area utilization of, and better matching in terms of area and performance between, the dies, greatly shortens the development time of new products and adds great diversity and freedom to product design.

Abstract: A bonding structure and a manufacturing method therefor. A first hybrid bonding structure is formed on a first wafer; an interconnection structure and a second hybrid bonding structure are formed on the front surface of a second wafer. The first wafer and the second wafer are bonded by means of the first hybrid bonding structure and the second hybrid bonding structure, a gasket electrically connected to the interconnection structure is formed on the back surface of the second wafer, and the interconnection structure below the gasket and a second conductive bonding pad in the second hybrid bonding structure are provided in a staggered manner in the horizontal direction. According to the solution, the interconnection structure and the second conductive bonding pad are arranged in a staggered manner, so that recesses generated by structural stacking are avoided, and device failure caused by the recesses is further avoided.

Abstract: A spinal image generation system based on the ultrasonic rubbing technique, comprises an acquisition unit and a processing unit. The system generates the ultrasonic rubbing based on two-dimensional spinal ultrasonic images. The image needs to include surface characteristic contour of the vertebra structure. The ultrasonic rubbing matches with a digital medical image through characteristic contour. After matching, a personalized spinal surface topographical map is established, which keeps real-time updating consistently with the intraoperative posture of the patient under surgical condition. A positioning and navigation system for spinal surgery based on the spinal image generation system, comprising a navigation module and the image generation system above. The navigation system can acquire a personalized spinal surface topographical map, which keeps real-time updating consistently with the intraoperative posture of the patient under surgical condition.

Abstract: The present disclosure discloses methods and apparatus for fatigue prediction based on analogue brain wave data, wherein one of the methods comprises: collecting an eye video sequence based on a video capture device; inputting the eye video sequence into a default fatigue discriminator to obtain predicted analogue brain wave data; and outputting the analogue brain wave data to a fatigue discriminant to discriminate a fatigue state. By adopting such a method for fatigue prediction based on analogue brain wave data described in the present disclosure, corresponding analogue brain wave data can be generated through acquiring eye image data, and the fatigue state can be predicted according to the analogue brain waves, so as to avoid tedious operation steps and improve the robustness and accuracy of the fatigue state detection, thereby greatly improving the user experience.

Abstract: The present disclosure discloses systems, methods and an apparatus for non-contact and eye-movement input of an elevator floor, which comprises: selecting a target camera according to a distance sensor installed on a button panel inside the elevator; triggering a corresponding target camera by using the distance sensor for face detection; standardizing a detected human face and locating a binocular position; inputting data of a standardized human face image and a binocular image into a preset posture discriminator to obtain a predicted head posture and an eyeball posture; according to the head posture and the eyeball posture, calculating a line-of-sight direction and a coordinate of an attention point, detecting whether a dwell time of the line-of-sight is greater than a preset time threshold, and, if so, triggering a button at the coordinate of the attention point.

Abstract: A wafer structure, a method for manufacturing the wafer structure, and a chip structure are provided. In a case that two wafers are bonded together, an opening extending through a substrate of one of the wafers is formed at a back surface of the wafer, and a concave-convex structure is formed in the dielectric layer under the opening. At least one of concave portions of the concave-convex structure extends to expose the interconnection layer of the wafer structure. A pad is formed on the concave-convex structure by filling the concave-convex structure, and the pad has the same concave-convex arrangement as the concave-convex structure. In this way, the pad has a concave-convex surface, such that a contact surface area of the pad is effectively increased without increasing a floor space of the pad.

Abstract: A multi-wafer stack structure and fabricating method thereof are disclosed. In the multi-wafer stack structure, the first interconnection layer is electrically connected to the second metal layer and the first metal layer via the first opening, the second interconnection layer is electrically connected to the first interconnection layer via the second openings, the third interconnection layer is electrically connected to the third metal layer via the third openings, and the second interconnection layer is in contact with the third interconnection layer, so that there is no need to reserve the wire pressure welding space between the wafers and a silicon substrate is eliminated, the overall device thickness of the multi-wafer stack package is reduced. Moreover, the design processing of the silicon substrate and a plurality of common pads on the silicon substrate is eliminated, thereby reducing the parasitic capacitance and power loss, and increasing the transmission speed.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In which a first opening and a second opening are vertically separated, and are no longer restricted by the condition that a deep upper opening needs to be filled with a thick photoresist when a TSV nested hole in vertical communication forms a middle opening and lower opening, thereby satisfying devices with different thicknesses requirements. The design is no longer restricted by the lateral process of the TSV nested hole, thereby enhancing the flexibility of the design. In the photolithography process, the deep hole does not need to be filled with the photoresist, the photoresist does not need to be thick, thereby reducing the complexity of the photolithography process and improving the exposure effect. The first metal layer and the second metal layer are directly led out via a first trench, thereby simplifying the process and reducing the production cost.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In the device, the isolation layer is used to prevent the first metal layer and the second metal layer which are over-etched and back-splashed from diffusing to a first substrate; and the isolation layer serves as a barrier layer to prevent an interconnection layer from diffusing into the first substrate. Further, the isolation layer includes a silicon nitride layer, which is advantageous for preventing the metal layers from back-splashing and diffusing to the sidewall of the first substrate. The isolation layer further includes a first silicon oxide layer and a second silicon oxide layer, wherein the second silicon oxide layer is used to protect the silicon nitride layer from being etched and consumed and the first silicon oxide layer is used to improve the adhesion between the silicon nitride layer and the first substrate.

Abstract: A wafer structure, a method for manufacturing the wafer structure, and a chip structure are provided. In a case that two wafers are bonded together, an opening extending through a substrate of one of the wafers is formed at a back surface of the wafer, and a concave-convex structure is formed in the dielectric layer under the opening. At least one of concave portions of the concave-convex structure extends to expose the interconnection layer of the wafer structure. A pad is formed on the concave-convex structure by filling the concave-convex structure, and the pad has the same concave-convex arrangement as the concave-convex structure. In this way, the pad has a concave-convex surface, such that a contact surface area of the pad is effectively increased without increasing a floor space of the pad.

Abstract: A spinal image generation system based on the ultrasonic rubbing technique, comprises an acquisition unit and a processing unit. The system generates the ultrasonic rubbing based on two-dimensional spinal ultrasonic images. The image needs to include surface characteristic contour of the vertebra structure. The ultrasonic rubbing matches with a digital medical image through characteristic contour. After matching, a personalized spinal surface topographical map is established, which keeps real-time updating consistently with the intraoperative posture of the patient under surgical condition. A positioning and navigation system for spinal surgery based on the spinal image generation system, comprising a navigation module and the image generation system above. The navigation system can acquire a personalized spinal surface topographical map, which keeps real-time updating consistently with the intraoperative posture of the patient under surgical condition.