Abstract: A semiconductor processing station is provided. The semiconductor processing station includes a first platform, a second platform and a vacuum tunnel, wherein the first platform has a first load lock and a first plurality of chambers, and the second platform has a second load lock and a second plurality of chambers, and the vacuum tunnel connects the first and the second load locks.

Abstract: A semiconductor processing station is provided. The semiconductor processing station includes a first platform, a second platform and a vacuum tunnel, wherein the first platform has a first load lock and a first plurality of chambers, and the second platform has a second load lock and a second plurality of chambers, and the vacuum tunnel connects the first and the second load locks.

Abstract: A semiconductor processing station is provided. The semiconductor processing station includes a first platform, a second platform and a vacuum tunnel, wherein the first platform has a first load lock and a first plurality of chambers, and the second platform has a second load lock and a second plurality of chambers, and the vacuum tunnel connects the first and the second load locks.

Abstract: One or more techniques or systems for ultra-high vacuum (UHV) wafer processing are provided herein. In some embodiments, a vacuum system includes one or more cluster tools connected via one or more bridges. For example, a first cluster tool is connected to a first bridge. Additionally, a second cluster tool is connected to a second bridge. In some embodiments, the first bridge is configured to connect the second cluster tool to the first cluster tool. In some embodiments, the second cluster tool is connected to the first bridge, thus forming a ‘tunnel’. In some embodiments, the second bridge comprises one or more facets configured to enable a connection to an additional process chamber or an additional cluster tool. In this manner, a more efficient UHV environment is provided, thus enhancing a yield associated with wafer processing, for example.

Abstract: One or more techniques or systems for ultra-high vacuum (UHV) wafer processing are provided herein. In some embodiments, a vacuum system includes one or more cluster tools connected via one or more bridges. For example, a first cluster tool is connected to a first bridge. Additionally, a second cluster tool is connected to a second bridge. In some embodiments, the first bridge is configured to connect the second cluster tool to the first cluster tool. In some embodiments, the second cluster tool is connected to the first bridge, thus forming a ‘tunnel’. In some embodiments, the second bridge comprises one or more facets configured to enable a connection to an additional process chamber or an additional cluster tool. In this manner, a more efficient UHV environment is provided, thus enhancing a yield associated with wafer processing, for example.

Abstract: A semiconductor processing station is provided. The semiconductor processing station includes a first platform, a second platform and a vacuum tunnel, wherein the first platform has a first load lock and a first plurality of chambers, and the second platform has a second load lock and a second plurality of chambers, and the vacuum tunnel connects the first and the second load locks.

Abstract: A semiconductor process includes polishing a substrate with a slurry in an enclosure. Polishing the substrate is stopped. First mist is injected into the enclosure, such that the first mist has at least about 80% of saturation of a liquid or gaseous solvent in a carrier within the enclosure.

Abstract: A semiconductor process includes polishing a substrate with a slurry in an enclosure. Polishing the substrate is stopped. First mist is injected into the enclosure, such that the first mist has at least about 80% of saturation of a liquid or gaseous solvent in a carrier within the enclosure.

Abstract: A semiconductor process includes polishing a substrate with a slurry in an enclosure. Polishing the substrate is stopped. First mist is injected into the enclosure, such that the first mist has at least about 80% of saturation of a liquid or gaseous solvent in a carrier within the enclosure.

Abstract: A system for cleaning a wafer. At least one first chuck roller is connected to a first roller base and includes a first annular groove. A second roller base opposes the first roller base. At least one second chuck roller is connected to the second roller base and includes a second annular groove. A sensing chuck roller is connected to the second roller base and includes a third annular groove corresponding to the first and second annular grooves. A cleaning member covers the third annular groove. A circumferential edge of the wafer is positioned in the first and second annular grooves and abuts the cleaning member. The first and second chuck rollers rotate the wafer, enabling the circumferential edge thereof to rub against the cleaning member.

Abstract: A semiconductor process includes polishing a substrate with a slurry in an enclosure. Polishing the substrate is stopped. First mist is injected into the enclosure, such that the first mist has at least about 80% of saturation of a liquid or gaseous solvent in a carrier within the enclosure.

Abstract: A system for cleaning a wafer. At least one first chuck roller is connected to a first roller base and includes a first annular groove. A second roller base opposes the first roller base. At least one second chuck roller is connected to the second roller base and includes a second annular groove. A sensing chuck roller is connected to the second roller base and includes a third annular groove corresponding to the first and second annular grooves. A cleaning member covers the third annular groove. A circumferential edge of the wafer is positioned in the first and second annular grooves and abuts the cleaning member. The first and second chuck rollers rotate the wafer, enabling the circumferential edge thereof to rub against the cleaning member.

Abstract: An electroplating anode including a substantially convex oxidizing surface for oxidation of metal atoms in a semiconductor wafer electroplating process. The electroplating anode of the present invention substantially prolongs the lifetime of the anode and contributes to the prevention of wafer contamination due to generation of potential wafer-contaminating precipitate particles during a wafer electroplating process.

Abstract: A calibration wafer which is suitable for calibrating alignment of a transfer robot blade with respect to wafers in a loadlock chamber or input shuttle. The calibration wafer includes a circular wafer body on which is provided a pair of spaced-apart blade alignment lines which are used to properly align the transfer robot blade. The invention further includes a calibration kit for calibrating alignment of a polishing head with a pedestal, including a base plate for placement on the pedestal; a calibration plate for placement on the base plate; and a calibration circle provided on the calibration plate for aligning the polishing head with the pedestal.

Abstract: A calibration wafer which is suitable for calibrating alignment of a transfer robot blade with respect to wafers in a loadlock chamber or input shuttle. The calibration wafer includes a circular wafer body on which is provided a pair of spaced-apart blade alignment lines which are used to properly align the transfer robot blade. The invention further includes a calibration kit for calibrating alignment of a polishing head with a pedestal, including a base plate for placement on the pedestal; a calibration plate for placement on the base plate; and a calibration circle provided on the calibration plate for aligning the polishing head with the pedestal.

Abstract: A novel apparatus and method for transporting semiconductor wafer substrates typically from a CMP apparatus to a scrubber cleaner in a dry state. The method includes providing a SMIF arm at the input port of the scrubber cleaner. After they are subjected to the CMP operation, the substrates are loaded into an enclosed substrate carrier such as a cassette or pod and transported to the SMIF arm of the scrubber cleaner at the input port, where the substrates are internalized and subjected to rinsing, scrubbing and drying steps in the cleaner. Automated transport of the dry substrates from the CMP apparatus to the scrubber cleaner in an enclosed substrate carrier prevents atmospheric particles from contaminating the substrates, prevents unnecessary use of manpower, and reduces or eliminates the possibility of breakage or damage to the substrates.

Abstract: A linear chemical mechanical polishing apparatus that is equipped with a programmable pneumatic support platen and a method for controlling the polishing profile on a wafer surface during a linear CMP process are disclosed. The programmable pneumatic support platen is positioned juxtaposed to a bottom surface of a continuous belt for the linear CMP apparatus and positioned corresponding to a position of the wafer carrier so as to force the polishing pad against the wafer surface to be polished. The support platen has a predetermined thickness, a plurality of apertures through the thickness and a plurality of openings in a top surface in fluid communication with a gas source through the plurality of apertures.

Abstract: A tensioning assembly for a polishing belt on a linear chemical mechanical polishing apparatus. The tensioning assembly comprises first and second rollers which are operably engaged by respective air cylinders and exert a selected degree of downward tension on the lower run of the horizontal polishing belt. A third roller biased typically by a spring pushes upwardly on the lower run of the belt between the first and second rollers. Accordingly, the first and second rollers, in conjunction with the third roller, tension the belt on the apparatus to maintain optimum material removal rates and uniformity. The degree of tension exerted on the belt can be varied according to stretching of the belt resulting from prolonged use.

Abstract: A ventilated platen/polishing pad assembly for chemical mechanical polishing copper conductors on a semiconductor wafer is disclosed. The ventilated platen is constructed by a platen having a multiplicity of apertures through a thickness of the platen, and a polishing pad that has a multiplicity of apertures for fluid communication with the multiplicity of apertures in the platen such that a gas can flow through the ventilated platen and the ventilated polishing pad to mix with a polishing slurry solution dispensed on top of the polishing pad. When an oxidizing gas is mixed with the slurry solution, the mass transfer process during the chemical mechanical polishing can be improved and thus improving the polishing uniformity of the copper surface.

Abstract: A tensioning assembly for a polishing belt on a linear chemical mechanical polishing apparatus. The tensioning assembly comprises first and second rollers which are operably engaged by respective air cylinders and exert a selected degree of downward tension on the lower run of the horizontal polishing belt. A third roller biased typically by a spring pushes upwardly on the lower run of the belt between the first and second rollers. Accordingly, the first and second rollers, in conjunction with the third roller, tension the belt on the apparatus to maintain optimum material removal rates and uniformity. The degree of tension exerted on the belt can be varied according to stretching of the belt resulting from prolonged use.