Abstract: A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.

Abstract: A method includes forming a spacer layer on a top surface and sidewalls of a patterned feature, wherein the patterned feature is overlying a base layer. A protection layer is formed to contact a top surface and a sidewall surface of the spacer layer. The horizontal portions of the protection layer are removed, wherein vertical portions of the protect layer remain after the removal. The spacer layer is etched to remove horizontal portions of the spacer layer, wherein vertical portions of the spacer layer remain to form parts of spacers.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: A method of making an optical bench includes forming a trench in a substrate and wherein the trench has a sloping side, forming a reflector layer over the sloping side, depositing a redistribution layer over the substrate, disposing an under bump metallization (UBM) layer over the redistribution layer, depositing a passivation layer over the redistribution layer and surrounding sidewalls of the UBM layer, and mounting an optical component over an uppermost portion of the substrate, wherein the optical component is electrically connected to a through substrate via (TSV) extending through the substrate. The reflector layer is configured to reflect an electromagnetic wave from the optical component, and wherein the optical component is mounted outside the trench.

Abstract: A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer.

Abstract: A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.

Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

Abstract: A method includes forming a spacer layer on a top surface and sidewalls of a patterned feature, wherein the patterned feature is overlying a base layer, A protection layer is formed to contact a top surface and a sidewall surface of the spacer layer. The horizontal portions of the protection layer are removed, wherein vertical portions of the protect layer remain after the removal. The spacer layer is etched to remove horizontal portions of the spacer layer, wherein vertical portions of the spacer layer remain to form parts of spacers.

Abstract: The present disclosure is generally related to semiconductor devices, and more particularly to a dielectric material formed in semiconductor devices. The present disclosure provides methods for forming a dielectric material layer by a cyclic spin-on coating process. In an embodiment, a method of forming a dielectric material on a substrate includes spin-coating a first portion of a dielectric material on a substrate, curing the first portion of the dielectric material on the substrate, spin-coating a second portion of the dielectric material on the substrate, and thermal annealing the dielectric material to form an annealed dielectric material on the substrate.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.

Abstract: Various self-aligned interconnect structures are disclosed herein. An exemplary interconnect structure includes a first dielectric layer disposed over a substrate; a first conductive feature disposed in the first dielectric layer; an etch stop layer disposed over a top surface of the first dielectric layer and a top surface of the first conductive feature; a second dielectric layer disposed over the first dielectric layer; and a second conductive feature disposed in the second dielectric layer. The top surface of the first conductive feature is lower than the top surface of the first dielectric layer. The etch stop layer includes a portion that extends between the top surface of the first conductive feature and the top surface of the first dielectric layer, on which the second conductive feature may or may not be disposed. In some implementations, the second conductive feature may be a via feature.

Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Abstract: A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide.

Abstract: A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the first dielectric layer. The structure further includes an etch stop layer over both the first dielectric layer and the exposed conductive line, and a second dielectric layer over the etch stop layer. The second dielectric layer and the etch stop layer provide a via hole that partially exposes the conductive line. The structure further includes a via disposed in the via hole, and another conductive line disposed over the via and coupled to the conductive line through the via. Methods of forming the multilayer interconnect structure are also disclosed. The etch stop layer reduces the lateral and vertical etching of the first and second dielectric layers when the via hole is misaligned due to overlay errors.

Abstract: Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.

Abstract: A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.

Abstract: A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening.

Abstract: An integrated circuit includes a substrate and at least one chip. Each chip is disposed over the substrate or the other chip. Solder bumps are disposed between the substrate and the at least one chip. An insulating film is disposed around the solder bumps and provides electrical insulation for the solder bumps except areas for interconnections. A thermally conductive underfill is disposed between the substrate, the at least one chip, and the solder bumps.