Patents by Inventor Tien-Lu Lin

Tien-Lu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12009254
    Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chen, Shih-Chuan Chiu, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin
  • Patent number: 12002756
    Abstract: A method of forming a semiconductor structure includes first forming a metal gate (MG) over a semiconductor layer, a gate spacer on a sidewall of the MG, and a source/drain (S/D) feature disposed in the semiconductor layer and adjacent to the MG, forming an S/D contact (MD) over the S/D feature, forming a first ILD layer over the MG and the MD, and subsequently patterning the first ILD layer to form an opening. The method further includes forming a metal layer in the opening, such that the metal layer contacts both the MG and the MD, removing a top portion of the metal layer to form a trench, filling the trench with a dielectric layer, and subsequently forming a second ILD layer over the dielectric layer.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240162094
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 16, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chuan CHIU, Jia-Chuan YOU, Chia-Hao CHANG, Chun-Yuan CHEN, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Publication number: 20240096961
    Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Shih-Chuan CHIU, Tien-Lu LIN, Yu-Ming LIN, Chia-Hao CHANG, Chih-Hao WANG, Jia-Chuan YOU
  • Patent number: 11908744
    Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes an isolation layer formed around the first fin structure and covering a sidewall of the first fin structure and a gate stack formed over the first fin structure and the isolation layer. The semiconductor device structure further includes a first source/drain structure formed over the first fin structure and spaced apart from the gate stack and a contact structure formed over the first source/drain structure. The semiconductor device structure includes a dielectric structure formed through the contact structure. In addition, the contact structure and the dielectric structure has a first slope interface that slopes downwardly from a top surface of the contact structure to a top surface of the isolation layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240055351
    Abstract: An interconnect structure including a dielectric structure, plugs, and conductive lines is provided. The dielectric structure is disposed on a substrate. The plugs are disposed in the dielectric structure. The conductive lines are disposed in the dielectric structure and are electrically connected to the plugs. The sidewall of at least one of the conductive lines is in direct contact with the dielectric structure.
    Type: Application
    Filed: September 13, 2022
    Publication date: February 15, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shou-Zen Chang, Mei Ling Ho, Tien-Lu Lin, Ming-Han Liao, Chia-Ming Wu, Jui-Neng Tu
  • Patent number: 11901238
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor, a conductive feature on the transistor, a dielectric layer over the conductive feature, and an electrical connection structure in the dielectric layer and on the conductive feature. The electrical connection structure includes a first grain of a first metal material and a first inhibition layer extending along a grain boundary of the first grain of the first metal material, the first inhibition layer is made of a second metal material, and the first metal material and the second metal material have different oxidation/reduction potentials.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chuan Chiu, Jia-Chuan You, Chia-Hao Chang, Chun-Yuan Chen, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11855144
    Abstract: A semiconductor device comprises a fin disposed on a substrate, a source/drain feature disposed over the fin, a silicide layer disposed over the source/drain feature, a seed metal layer disposed over the silicide layer and wrapping around the source/drain feature, and a metal layer disposed on the silicide layer, where the metal layer contacts the seed metal layer.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Jia-Chuan You, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11842962
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect arranged within an inter-level dielectric (ILD) layer. The first interconnect has opposing sidewalls that are both laterally separated from closest neighboring interconnects within the ILD layer by one or more air-gaps along a cross-sectional view. A second interconnect is arranged within the ILD layer. The ILD layer laterally contacts opposing sidewalls of the second interconnect as viewed along the cross-sectional view.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-I Yang, Cheng-Chi Chuang, Yung-Chih Wang, Tien-Lu Lin
  • Publication number: 20230395698
    Abstract: Disclosed are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a first dielectric layer, a first gate, a second dielectric layer, and a second gate. The first dielectric layer is located on the substrate. The first gate is located on the first dielectric layer. The second dielectric layer is located on the substrate. The second gate is located on the second dielectric layer. A bottom surface of the second gate and a bottom surface of the first gate are located on different planes.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 7, 2023
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Tien-Lu Lin, Ying-Chia Lin, Chuen-Jiunn Shyu, Shou-Zen Chang
  • Publication number: 20230386911
    Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Chun-Yuan Chen, Shih-Chuan Chiu, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin
  • Publication number: 20230343633
    Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 26, 2023
    Inventors: Lin-Yu HUANG, Sheng-Tsung WANG, Chia-Hao CHANG, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Publication number: 20230335584
    Abstract: A semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a gate electrode layer formed over a semiconductor substrate and capped with a conductive capping layer. The semiconductor device structure also includes an insulating capping stack having a lower surface that faces and is spaced apart from an upper surface of the conductive capping layer. In addition, the semiconductor device structure includes gate spacers formed over the semiconductor substrate and covering opposing sidewalls of the gate electrode layer, the conductive capping layer, and the insulating capping stack.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tien-Lu LIN, Che-Chen WU, Chia-Lin CHUANG, Yu-Ming LIN, Chia-Hao CHANG
  • Publication number: 20230282720
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.
    Type: Application
    Filed: April 24, 2023
    Publication date: September 7, 2023
    Inventors: Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20230261109
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a contact over a source/drain region of a fin structure, a gate stack over a channel region of the fin structure, a first mask layer covering the gate stack, and a second mask layer covering the contact. A side surface of the first mask layer is direct contact with a side surface of the second mask layer, and the first mask layer includes a portion directly below the second mask layer.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 17, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lin-Yu HUANG, Jia-Chuan YOU, Chia-Hao CHANG, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Publication number: 20230253480
    Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Patent number: 11715761
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a pair of source/drain features formed in a semiconductor substrate and a gate stack formed over a portion of the semiconductor substrate that is between the pair of source/drain features. The semiconductor device structure also includes gate spacers extend along opposing sidewalls of the gate stack and protrude above an upper surface of the gate stack. Additionally, the semiconductor device structure includes a first capping layer formed over the gate stack and spaced apart from the upper surface of the gate stack by a gap. Opposing sidewalls of the first capping layer are covered by portions of the gate spacers that protrude above the upper surface of the gate stack.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tien-Lu Lin, Che-Chen Wu, Chia-Lin Chuang, Yu-Ming Lin, Chia-Hao Chang
  • Publication number: 20230215948
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Inventors: Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11694921
    Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11658244
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack and a contact over a fin structure, a gate spacer layer between the gate stack and the contact, a first mask layer over the gate stack, and a second mask layer over the contact. The first mask layer includes a protruding portion sandwiched between an upper portion of the second mask layer and the gate spacer layer.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lin-Yu Huang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang