Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.

Abstract: A semiconductor device includes a substrate, a liner, and an isolation structure. The substrate has at least one first semiconductor fin and at least one second semiconductor fin. The liner is disposed on at least one sidewall of the second semiconductor fin. The isolation structure is disposed over the substrate, in which the isolation structure is in contact with the first semiconductor fin and the liner.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer over a first substrate, and the dielectric layer has a plurality of openings. The method also includes forming a first graphene layer in the openings and over the first dielectric layer, and forming an insulating layer in the first graphene layer. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second graphene layer in and over the second dielectric layer. A portion of the second graphene layer interfaces with a portion of the first graphene layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric structure over a substrate, and a first interconnect structure arranged within the dielectric structure. A lower interconnect structure is arranged within the dielectric structure. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials. The first interconnect structure continuously extends from directly over a topmost surface of the lower interconnect structure facing away from the substrate to along opposing outer sidewalls of the lower interconnect structure.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first metal wire arranged within an inter-level dielectric (ILD) layer over a substrate. A second metal wire is arranged within the ILD layer and is laterally separated from the first metal wire by an air-gap. A dielectric layer is arranged over the first metal wire and the second metal wire. The dielectric layer has a curved surface along a top of the air-gap. The curved surface of the dielectric layer is a smooth curved surface that continuously extends between opposing sides of the air-gap. A via is disposed on and over the second metal wire.

Abstract: A method for forming a fin field effect transistor device structure includes forming fin structures over a substrate. The method also includes forming a gate structure across the fin structures. The method also includes forming source/drain epitaxial structures over the fin structures. The method also includes forming blocking structures between the source/drain epitaxial structures. The method also includes depositing contact structures over the source/drain epitaxial structures and between the blocking structures. The method also includes removing a top portion of the blocking structures. The method also includes depositing an etch stop layer over the blocking structures and the contact structures, so that an air gap is formed between the etch stop layer and the blocking structure.

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The method includes forming a dielectric layer over the first epitaxial structure, the second epitaxial structure, and the semiconductor substrate. The method includes forming a first mask layer over the dielectric layer and between the first epitaxial structure and the second epitaxial structure. The method includes forming a second mask layer over the dielectric layer and the first mask layer. The method includes partially removing the dielectric layer covering the first epitaxial structure and the second epitaxial structure. The method includes removing the first mask layer. The method includes forming a first conductive layer and a second conductive layer respectively in the first recess and the second recess.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first metal wire arranged within an inter-level dielectric (ILD) layer over a substrate and laterally separated in a first direction from a first closest air-gap by a first distance. A second metal wire is arranged within the ILD layer and is laterally separated in the first direction from a second closest air-gap by a second distance that is larger than the first distance. A via is disposed on an upper surface of the second metal wire.

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.

Abstract: The present disclosure provides a method for semiconductor fabrication. The method includes epitaxially growing source/drain feature on a fin; forming a silicide layer over the epitaxial source/drain feature; forming a seed metal layer on the silicide layer; forming a contact metal layer over the seed metal layer using a bottom-up growth approach; and depositing a fill metal layer over the contact metal layer.

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

Abstract: A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.

Abstract: A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.

Abstract: A method of forming a semiconductor device includes providing a device having a gate stack including a metal gate layer. The device further includes a spacer layer disposed on a sidewall of the gate stack and a source/drain feature adjacent to the gate stack. The method further includes performing a first etch-back process to the metal gate layer to form an etched-back metal gate layer. In some embodiments, the method includes depositing a metal layer over the etched-back metal gate layer. In some cases, a semiconductor layer is formed over both the metal layer and the spacer layer to provide a T-shaped helmet layer over the gate stack and the spacer layer.

Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.