Patents by Inventor Tien-Yu Lee

Tien-Yu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930611
    Abstract: An integrated circuit assembly having an improved solder connection, and methods for fabricating the same are provided that utilize platelets within the solder connections to inhibit solder connection failure, thus providing a more robust solder interface. In one example, an integrated circuit assembly is provided that includes a package substrate having a first plurality of contact pads exposed on a first surface of the package substrate and a second plurality of contact pads exposed on a second surface of the package substrate. The second plurality of contact pads have a pitch that is greater than a pitch of the first plurality of contact pads. Interconnect circuitry is disposed in the package substrate and couples the first and second pluralities of contact pads. At least a first contact pad of the second plurality of contact pads includes a solder ball disposed directly in contact with a palladium layer.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 23, 2021
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Tien-Yu Lee
  • Publication number: 20200235079
    Abstract: A chip-scale LED package structure includes a white light emitting unit for emitting a white light, a red flip-chip LED for emitting a red light, a green flip-chip LED for emitting a green light, a blue flip-chip LED for emitting a blue light, and an encapsulation layer. The encapsulation includes an encapsulation resin and a plurality of refractive particles distributed in the encapsulation resin. The encapsulation layer encapsulates the white light emitting unit, the red flip-chip LED, the green flip-chip LED, and the blue flip-chip LED. Moreover, electrodes of the white light emitting unit, electrodes of the red flip-chip LED, electrodes of the green flip-chip LED, and electrodes of the blue flip-chip LED are exposed from the encapsulation layer.
    Type: Application
    Filed: December 18, 2019
    Publication date: July 23, 2020
    Inventors: TIEN-YU LEE, CHIH-YUAN CHEN, WEI-LUN TSAI, CHIEN-TUNG HUANG, WEI-HSUN HSU, WEI-CHIEN HUNG
  • Publication number: 20200176648
    Abstract: A light emitting package structure includes: a light emitting chip, an encapsulant covering the light emitting chip and having an anti-adhesion upper surface and an anti-adhesion surrounding surface. A method of manufacturing a light emitting package structure is further provided and includes: configuring a plurality of light emitting chips on a temporary carrier; forming an encapsulant to cover the plurality of light emitting chips; cutting the encapsulant to form the independent light emitting package structure; and surface treating the cut encapsulant such that the encapsulant has an anti-adhesion upper surface and an anti-adhesion surrounding surface.
    Type: Application
    Filed: October 4, 2019
    Publication date: June 4, 2020
    Inventors: CHIH-YUAN CHEN, TIEN-YU LEE, CHIEN-TUNG HUANG, WEI-LUN TSAI
  • Publication number: 20200105642
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Gamal Refai-Ahmed, Henley Liu, Myongseob Kim, Tien-Yu Lee, Suresh Ramalingam, Cheang-Whang Chang
  • Patent number: 10529645
    Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: January 7, 2020
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Henley Liu, Tien-Yu Lee, Gamal Refai-Ahmed, Myongseob Kim, Ferdinand F. Fernandez, Ivor G. Barber, Suresh Ramalingam
  • Patent number: 10527670
    Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: January 7, 2020
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Ivor G. Barber, Suresh Ramalingam, Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, David M. Mahoney, Mohsen H. Mardi
  • Patent number: 10319606
    Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a package substrate having a plurality of solder balls coupled to a plurality of contact pads. The package substrate includes a solder mask having a plurality of stepped openings, a plurality of contact pads, and circuitry disposed in the package substrate and coupled to the plurality of contact pads. The solder mask defines a top side of the package substrate. The stepped openings expose the contact pads through solder mask.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, Ivor G. Barber, Suresh Ramalingam
  • Publication number: 20180358280
    Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 13, 2018
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Henley Liu, Tien-Yu Lee, Gamal Refai-Ahmed, Myongseob Kim, Ferdinand F. Fernandez, Ivor G. Barber, Suresh Ramalingam
  • Patent number: 10096502
    Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: October 9, 2018
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Mohsen H. Mardi, Tien-Yu Lee, Ivor G. Barber, Cheang-Whang Chang, Jaspreet Singh Gandhi
  • Publication number: 20180284187
    Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.
    Type: Application
    Filed: March 28, 2017
    Publication date: October 4, 2018
    Applicant: Xilinx, Inc.
    Inventors: Gamal Refai-Ahmed, Ivor G. Barber, Suresh Ramalingam, Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, David M. Mahoney, Mohsen H. Mardi
  • Patent number: 10043730
    Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: August 7, 2018
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Tien-Yu Lee, Ferdinand F. Fernandez, Suresh Ramalingam, Ivor G. Barber, Inderjit Singh, Nael Zohni
  • Publication number: 20180144963
    Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.
    Type: Application
    Filed: November 23, 2016
    Publication date: May 24, 2018
    Applicant: Xilinx, Inc.
    Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Mohsen H. Mardi, Tien-Yu Lee, Ivor G. Barber, Cheang-Whang Chang, Jaspreet Singh Gandhi
  • Patent number: 9653669
    Abstract: An LED package structure includes a base, an LED chip disposed on the base, at least one metal wire, a phosphor sheet, and an encapsulation resin disposed in the base and encapsulating the LED chip, the metal wire, and the phosphor sheet. The LED chip has at least one electrode thereon. The metal wire has an apex and a loop height being defined by the apex. The metal wire is electrically connected to the electrode and the base. The phosphor sheet includes a B-stage resin and a plurality of phosphor powders mixed therewith. The phosphor sheet is adhered to the LED chip by the B-stage resin capable of viscosity and covers the top surface, the side surface, and the electrode of the LED chip. A thickness of the phosphor sheet is smaller than the loop height, and the apex of the metal wire is exposed from the phosphor sheet.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: May 16, 2017
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chih-Yuan Chen, Tien-Yu Lee
  • Publication number: 20170092619
    Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 30, 2017
    Applicant: Xilinx, Inc.
    Inventors: Gamal Refai-Ahmed, Tien-Yu Lee, Ferdinand F. Fernandez, Suresh Ramalingam, Ivor G. Barber, Inderjit Singh, Nael Zohni
  • Publication number: 20160336498
    Abstract: An LED package structure includes a base, an LED chip disposed on the base, at least one metal wire, a phosphor sheet, and an encapsulation resin disposed in the base and encapsulating the LED chip, the metal wire, and the phosphor sheet. The LED chip has at least one electrode thereon. The metal wire has an apex and a loop height being defined by the apex. The metal wire is electrically connected to the electrode and the base. The phosphor sheet includes a B-stage resin and a plurality of phosphor powders mixed therewith. The phosphor sheet is adhered to the LED chip by the B-stage resin capable of viscosity and covers the top surface, the side surface, and the electrode of the LED chip. A thickness of the phosphor sheet is smaller than the loop height, and the apex of the metal wire is exposed from the phosphor sheet.
    Type: Application
    Filed: July 26, 2016
    Publication date: November 17, 2016
    Inventors: CHIH-YUAN CHEN, TIEN-YU LEE
  • Patent number: 9455387
    Abstract: A manufacturing method of an LED package structure includes the steps of providing a base; disposing an LED chip on the base; electrically connecting the base and the LED chip by at least one metal wire, wherein the metal wire has an apex, and a height between the apex and a top surface of the LED chip is defined as a loop height; adhering a first phosphor sheet to the LED chip by a B-stage resin of the first phosphor sheet, wherein the first phosphor sheet covers the top surface, the side surface, and the electrode of the LED chip, the thickness of the first phosphor sheet is smaller than the loop height, and the apex of the metal wire is exposed from the first phosphor sheet; and disposing an encapsulation resin in the base to encapsulate the LED chip, the metal wire, and the first phosphor sheet.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: September 27, 2016
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chih-Yuan Chen, Tien-Yu Lee
  • Publication number: 20160260877
    Abstract: A manufacturing method of an LED package structure includes the steps of providing a base; disposing an LED chip on the base; electrically connecting the base and the LED chip by at least one metal wire, wherein the metal wire has an apex, and a height between the apex and a top surface of the LED chip is defined as a loop height; adhering a first phosphor sheet to the LED chip by a B-stage resin of the first phosphor sheet, wherein the first phosphor sheet covers the top surface, the side surface, and the electrode of the LED chip, the thickness of the first phosphor sheet is smaller than the loop height, and the apex of the metal wire is exposed from the first phosphor sheet; and disposing an encapsulation resin in the base to encapsulate the LED chip, the metal wire, and the first phosphor sheet.
    Type: Application
    Filed: August 5, 2015
    Publication date: September 8, 2016
    Inventors: CHIH-YUAN CHEN, TIEN-YU LEE
  • Patent number: 9204542
    Abstract: An apparatus includes a package substrate for a first SSIT product with a first top die configuration, wherein the package substrate is compatible with a second SSIT product with a second top die configuration, and wherein the first top die configuration is different from the second top die configuration.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: December 1, 2015
    Assignee: XILINX, INC.
    Inventors: Tien-Yu Lee, Rafael C. Camarota
  • Publication number: 20120194067
    Abstract: A LED device includes a base structure having a receiving space, a light-emitting chip, an encapsulating structure, and a phosphor layer. The receiving space is defined by an inner bottom surface of the base structure and an inner side wall surrounding the inner bottom surface. The light-emitting chip is mounted on the bottom of the receiving space. The encapsulating structure is filled into the receiving space to cover the light-emitting chip. The phosphor layer is formed on the encapsulating structure. The dimension of the phosphor layer is more than the dimension of the receiving space and less than 1.5 times that of the receiving space, so as to mount on the top surface of the base structure.
    Type: Application
    Filed: April 13, 2012
    Publication date: August 2, 2012
    Applicants: LITE-ON TECHNOLOGY CORPORATION, SILITEK ELECTRONIC (GUANGZHOU) CO., LTD.
    Inventors: CHIA-HAO WU, TIEN-YU LEE
  • Patent number: 8216864
    Abstract: A LED device includes a base structure having a receiving space, a light-emitting chip, an encapsulating structure, and a phosphor layer. The receiving space is defined by an inner bottom surface of the base structure and an inner side wall surrounding the inner bottom surface. The light-emitting chip is mounted on the bottom of the receiving space. The encapsulating structure is filled into the receiving space to cover the light-emitting chip. The phosphor layer is formed on the encapsulating structure. The dimension of the phosphor layer is more than the dimension of the receiving space and less than 1.5 times that of the receiving space, so as to mount on the top surface of the base structure.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: July 10, 2012
    Assignees: Silitek Electronic (Guangzhou) Co., Ltd., Lite-On Technology Corporation
    Inventors: Chia-Hao Wu, Tien-Yu Lee