Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

Abstract: A chip package assembly having robust solder connections are described herein. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die and a package substrate. Solder pads are arranged to connect to pillars of the IC die via solder connections. Solder resist in the corners of the package substrate and surrounding the solder connections may be inhibited from cracking isolating the portion of the solder resist surrounding the solder pads and/or by providing an offset between centerlines of the pillars and solder pads.

Abstract: A chip-scale LED package structure includes a white light emitting unit for emitting a white light, a red flip-chip LED for emitting a red light, a green flip-chip LED for emitting a green light, a blue flip-chip LED for emitting a blue light, and an encapsulation layer. The encapsulation includes an encapsulation resin and a plurality of refractive particles distributed in the encapsulation resin. The encapsulation layer encapsulates the white light emitting unit, the red flip-chip LED, the green flip-chip LED, and the blue flip-chip LED. Moreover, electrodes of the white light emitting unit, electrodes of the red flip-chip LED, electrodes of the green flip-chip LED, and electrodes of the blue flip-chip LED are exposed from the encapsulation layer.

Abstract: An integrated circuit assembly having an improved solder connection, and methods for fabricating the same are provided that utilize platelets within the solder connections to inhibit solder connection failure, thus providing a more robust solder interface. In one example, an integrated circuit assembly is provided that includes a package substrate having a first plurality of contact pads exposed on a first surface of the package substrate and a second plurality of contact pads exposed on a second surface of the package substrate. The second plurality of contact pads have a pitch that is greater than a pitch of the first plurality of contact pads. Interconnect circuitry is disposed in the package substrate and couples the first and second pluralities of contact pads. At least a first contact pad of the second plurality of contact pads includes a solder ball disposed directly in contact with a palladium layer.

Abstract: A chip-scale LED package structure includes a white light emitting unit for emitting a white light, a red flip-chip LED for emitting a red light, a green flip-chip LED for emitting a green light, a blue flip-chip LED for emitting a blue light, and an encapsulation layer. The encapsulation includes an encapsulation resin and a plurality of refractive particles distributed in the encapsulation resin. The encapsulation layer encapsulates the white light emitting unit, the red flip-chip LED, the green flip-chip LED, and the blue flip-chip LED. Moreover, electrodes of the white light emitting unit, electrodes of the red flip-chip LED, electrodes of the green flip-chip LED, and electrodes of the blue flip-chip LED are exposed from the encapsulation layer.

Abstract: A light emitting package structure includes: a light emitting chip, an encapsulant covering the light emitting chip and having an anti-adhesion upper surface and an anti-adhesion surrounding surface. A method of manufacturing a light emitting package structure is further provided and includes: configuring a plurality of light emitting chips on a temporary carrier; forming an encapsulant to cover the plurality of light emitting chips; cutting the encapsulant to form the independent light emitting package structure; and surface treating the cut encapsulant such that the encapsulant has an anti-adhesion upper surface and an anti-adhesion surrounding surface.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.

Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a package substrate having a plurality of solder balls coupled to a plurality of contact pads. The package substrate includes a solder mask having a plurality of stepped openings, a plurality of contact pads, and circuitry disposed in the package substrate and coupled to the plurality of contact pads. The solder mask defines a top side of the package substrate. The stepped openings expose the contact pads through solder mask.

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.

Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.

Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.

Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.

Abstract: An LED package structure includes a base, an LED chip disposed on the base, at least one metal wire, a phosphor sheet, and an encapsulation resin disposed in the base and encapsulating the LED chip, the metal wire, and the phosphor sheet. The LED chip has at least one electrode thereon. The metal wire has an apex and a loop height being defined by the apex. The metal wire is electrically connected to the electrode and the base. The phosphor sheet includes a B-stage resin and a plurality of phosphor powders mixed therewith. The phosphor sheet is adhered to the LED chip by the B-stage resin capable of viscosity and covers the top surface, the side surface, and the electrode of the LED chip. A thickness of the phosphor sheet is smaller than the loop height, and the apex of the metal wire is exposed from the phosphor sheet.

Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.

Abstract: An LED package structure includes a base, an LED chip disposed on the base, at least one metal wire, a phosphor sheet, and an encapsulation resin disposed in the base and encapsulating the LED chip, the metal wire, and the phosphor sheet. The LED chip has at least one electrode thereon. The metal wire has an apex and a loop height being defined by the apex. The metal wire is electrically connected to the electrode and the base. The phosphor sheet includes a B-stage resin and a plurality of phosphor powders mixed therewith. The phosphor sheet is adhered to the LED chip by the B-stage resin capable of viscosity and covers the top surface, the side surface, and the electrode of the LED chip. A thickness of the phosphor sheet is smaller than the loop height, and the apex of the metal wire is exposed from the phosphor sheet.

Abstract: A manufacturing method of an LED package structure includes the steps of providing a base; disposing an LED chip on the base; electrically connecting the base and the LED chip by at least one metal wire, wherein the metal wire has an apex, and a height between the apex and a top surface of the LED chip is defined as a loop height; adhering a first phosphor sheet to the LED chip by a B-stage resin of the first phosphor sheet, wherein the first phosphor sheet covers the top surface, the side surface, and the electrode of the LED chip, the thickness of the first phosphor sheet is smaller than the loop height, and the apex of the metal wire is exposed from the first phosphor sheet; and disposing an encapsulation resin in the base to encapsulate the LED chip, the metal wire, and the first phosphor sheet.