Patents by Inventor Tiesheng Li
Tiesheng Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7875541Abstract: Fabricating a semiconductor device includes forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate having a gate top surface that extends substantially above the top substrate surface at least in center region of the trench opening, the gate having a vertical edge that includes an extended portion, the extended portion extending above the trench opening and being substantially aligned with the trench wall.Type: GrantFiled: December 22, 2009Date of Patent: January 25, 2011Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Sung-Shan Tai, Tiesheng Li, Anup Bhalla, Hong Chang, Moses Ho
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Publication number: 20100302810Abstract: Voltage converters with integrated low power leaker device and associated methods are disclosed herein. In one embodiment, a voltage converter includes a switch configured to convert a first electrical signal into a second electrical signal different than the first electrical signal. The voltage converter also includes a controller operatively coupled to the switch and a leaker device electrically coupled to the controller. The controller is configured to control the on and off gates of the switch, and the leaker device is configured to deliver power to the controller. The leaker device and the switch are formed on a first semiconductor substrate, and the controller is formed on second semiconductor substrate separate from the first semiconductor substrate.Type: ApplicationFiled: May 28, 2009Publication date: December 2, 2010Inventors: Michael R. Hsing, Ognjen Milic, Tiesheng Li
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Publication number: 20100291744Abstract: Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.Type: ApplicationFiled: July 30, 2010Publication date: November 18, 2010Applicant: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Yeeheng Lee, Hong Chang, Tiesheng Li, John Chen, Anup Bhalla
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Patent number: 7800169Abstract: A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.Type: GrantFiled: September 11, 2007Date of Patent: September 21, 2010Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Anup Bhalla, Sik Lui, Tiesheng Li
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Patent number: 7795108Abstract: A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut DL of the test structure is determined from the signal and an etch depth DT is determined from DL. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.Type: GrantFiled: March 6, 2009Date of Patent: September 14, 2010Assignee: Alpha & Omega Semiconductor, LtdInventors: Tiesheng Li, Yu Wang, Yingying Lou, Anup Bhalla
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Patent number: 7767526Abstract: Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.Type: GrantFiled: January 29, 2009Date of Patent: August 3, 2010Assignee: Alpha & Omega Semiconductor IncorporatedInventors: Yeeheng Lee, Hong Chang, Tiesheng Li, John Chen, Anup Bhalla
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Publication number: 20100190307Abstract: Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.Type: ApplicationFiled: January 29, 2009Publication date: July 29, 2010Applicant: ALPHA & OMEGA SEMICONDUCTOR, INCInventors: Yeeheng Lee, Hong Chang, Tiesheng Li, John Chen, Anup Bhalla
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Publication number: 20100148246Abstract: This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region.Type: ApplicationFiled: February 9, 2010Publication date: June 17, 2010Inventors: Anup Bhalla, Daniel Ng, Tiesheng Li, Sik K. Lui
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Publication number: 20100105182Abstract: Fabricating a semiconductor device includes forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate having a gate top surface that extends substantially above the top substrate surface at least in center region of the trench opening, the gate having a vertical edge that includes an extended portion, the extended portion extending above the trench opening and being substantially aligned with the trench wall.Type: ApplicationFiled: December 22, 2009Publication date: April 29, 2010Inventors: Sung-Shan Tai, Tiesheng Li, Anup Bhalla, Hong Chang, Moses Ho
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Publication number: 20100084707Abstract: This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.Type: ApplicationFiled: December 9, 2009Publication date: April 8, 2010Inventors: Yu Wang, Tiesheng Li, Sung-Shan Tai, Hong Chang
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Patent number: 7683369Abstract: A structure is disclosed for measuring body pinch resistance Rp of trench MOSFET arrays on a wafer. The trench MOSFET array has a common drain layer of first conductivity type and a 2D-trench MOSFET array atop the common drain layer. The 2D-trench MOSFET array has an interdigitated array of source-body columns and gate trench columns. Each source-body column has a bottom body region of second conductivity type with up-extending finger structures. Each source-body column has top source regions of first conductivity type bridging the finger structures. The structure includes: a) A source-body column wherein each finger structure of the bottom body region has a formed top contact electrode. b) Two gate trench columns flank the source-body column and both have a formed top common gate contact electrode. Upon connection of the structure to external voltage/current measurement devices, Rp can be measured while mimicking the parasitic effect of neighboring trench MOSFETs.Type: GrantFiled: April 10, 2008Date of Patent: March 23, 2010Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Moses Ho, Tiesheng Li, Il Kwan Lee
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Patent number: 7667264Abstract: A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a gate disposed in the trench, having a gate top surface that extends substantially above the body top surface. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.Type: GrantFiled: September 27, 2004Date of Patent: February 23, 2010Assignee: Alpha and Omega Semiconductor LimitedInventors: Sung-Shan Tai, Tiesheng Li, Anup Bhalla, Hong Chang, Moses Ho
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Patent number: 7659570Abstract: This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region.Type: GrantFiled: May 9, 2005Date of Patent: February 9, 2010Assignee: Alpha & Omega Semiconductor Ltd.Inventors: Anup Bhalla, Daniel Ng, Tiesheng Li, Sik K. Lui
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Patent number: 7632733Abstract: This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.Type: GrantFiled: April 29, 2006Date of Patent: December 15, 2009Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Yu Wang, Tiesheng Li, Sung-Shan Tai, Hong Chang
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Patent number: 7605425Abstract: A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall.Type: GrantFiled: September 11, 2007Date of Patent: October 20, 2009Assignee: Alpha & Omega Semiconductor LimitedInventors: Anup Bhalla, Sik Lui, Tiesheng Li
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Publication number: 20090256149Abstract: A structure is disclosed for measuring body pinch resistance Rp of trench MOSFET arrays on a wafer. The trench MOSFET array has a common drain layer of first conductivity type and a 2D-trench MOSFET array atop the common drain layer. The 2D-trench MOSFET array has an interdigitated array of source-body columns and gate trench columns. Each source-body column has a bottom body region of second conductivity type with up-extending finger structures. Each source-body column has top source regions of first conductivity type bridging the finger structures. The structure includes: a) A source-body column wherein each finger structure of the bottom body region has a formed top contact electrode. b) Two gate trench columns flank the source-body column and both have a formed top common gate contact electrode. Upon connection of the structure to external voltage/current measurement devices, Rp can be measured while mimicking the parasitic effect of neighboring trench MOSFETs.Type: ApplicationFiled: April 10, 2008Publication date: October 15, 2009Inventors: Moses Ho, Tiesheng Li, Il Kwan Lee
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Publication number: 20090224316Abstract: A semiconductor device includes a drain, a body disposed over the drain, a source embedded in the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench extending through the source into the body, a conductive contact layer disposed along at least a portion of a source body contact trench sidewall and in contact with at least a portion of the source, and a trench filling material disposed in the source body contact trench and overlaying at least a portion of the conductive contact layer.Type: ApplicationFiled: March 31, 2009Publication date: September 10, 2009Inventors: Anup Bhalla, Sik Lui, Tiesheng Li
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Publication number: 20090166621Abstract: A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut DL of the test structure is determined from the signal and an etch depth DT is determined from DL. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.Type: ApplicationFiled: March 6, 2009Publication date: July 2, 2009Applicant: ALPHA & OMEGA SEMICONDUCTOR, LTD.Inventors: Tiesheng Li, Yu Wang, Yingying Lou, Anup Bhalla
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Publication number: 20090148995Abstract: This invention discloses an improved method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) device. The method includes a step of opening a trench in substrate and covering trench walls of the trench with a linen layer followed by removing a portion of the linen layer from a bottom portion of the trench. The method further includes a step of opening a round hole by applying an isotropic substrate etch on the bottom portion of the trench with the round hole extending laterally from the trench walls. The method further includes a step of filling the trench and the round hole at the bottom of the trench with a gate material followed by applying a time etch to removed the gate material from a top portion of the trench whereby the gate material only filling the round hole up to a lateral expansion point of the round hole.Type: ApplicationFiled: February 9, 2009Publication date: June 11, 2009Inventors: Hong Chang, Sung-Shan Tai, Tiesheng Li, Yu Wang
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Patent number: 7521332Abstract: A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut DL of the test structure is determined from the signal and an etch depth DT is determined from DL. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.Type: GrantFiled: March 23, 2007Date of Patent: April 21, 2009Assignee: Alpha & Omega Semiconductor, LtdInventors: Tiesheng Li, Yu Wang, Yingying Lou, Anup Bhalla