Abstract: In a digital signal processing system, a logarithmic arithmetic logic unit which selectively performs multiply/accumulate operations of operands in logarithmic number representation. Direct feed through of operands through an adder/subtractor circuit, even when an addition or subtraction is not effected, eliminates external bypass circuitry. A method for adding and subtracting operands in logarithmic number representation. An adder/subtractor circuit which efficiently effects addition and subtraction of operands in logarithmic number representation over a wide dynamic range.

Abstract: A modulo arithmetic unit and method for providing a sum of first and second numbers is provided. In one form, a first adder calculates a first sum which is equal to the arithmetic sum of the first and second numbers. A second adder is provided for adding the first number to an offset value equal to (2.sup.X -M), where X defines the number of bits of the number system used, M is a predetermined modulus and X and M are integers. A third adder operates in parallel with the first adder to calculate the sum of the output value of the second adder and the second operand to provide a second output sum and a carry output bit. In another form, only two adders are utilized wherein the first adder calculates a first output sum of the first and second numbers, and the second adder calculates the sum of the first output sum and the offset value. Both illustrated forms utilize a multiplexer which outputs one of the two calculated output sums depending upon whether a wraparound of an upper modulus boundary occurred.

Abstract: In a digital signal processing system, a logarithmic arithmetic logic unit is provided which selectively performs multiply/accumulate operations of operands in logarithmic number representation. Direct feed through of operands through an adder/subtractor circuit, even when an addition or subtraction is not effected, eliminates external bypass circuitry. A method for adding and subtracting operands in logarithmic number representation is provided. An adder/subtractor circuit which efficiently effects addition and subtraction of operands in logarithmic number representation over a wide dynamic range is provided.

Abstract: CVSD modulation is detected by applying a digital signal containing CVSD information to a digital filter that is in the CVSD loop that includes a syllabic filter and a rule circuit. The digital filter includes voltage-operated switches that switch one of two voltages to a resistor network and thereby combine multiplication and digital filtering. The output of the digital filter is the output of the circuit.

Abstract: An n-ordered digital filter is disclosed in the form of a Partial Autocorrelation (PARCOR) lattice structure having two multipliers and two adders. Time multiplexing eliminates the use of individual multipliers and adders for each order of the filter. Speech synthesis of a time varying digital input signal is provided by performing n stages of Linear Predictive Coding (LPC) difference equation operation, where n is an integer. Delay means and storage registers minimize the control circuitry and circuit die size to calculate the difference equations to an nth order.