Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to mask structures and methods of manufacture. The method includes determining a plane through a frontside surface and a backside surface of a mask, each plane representing a flatness of the frontside surface and the backside surface, respectively; subtracting, using at least one computing device, a difference between the plane of the frontside surface and the plane of the backside surface to find a thickness variation; generating, using the at least one computing device, a fitting to fit the thickness variation; and subtracting, using the at least one computing device, the fitting from the thickness variation to generate a residual structure for collecting a residual flatness measurement.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to mask structures and methods of manufacture. The method includes determining a plane through a frontside surface and a backside surface of a mask, each plane representing a flatness of the frontside surface and the backside surface, respectively; subtracting, using at least one computing device, a difference between the plane of the frontside surface and the plane of the backside surface to find a thickness variation; generating, using the at least one computing device, a fitting to fit the thickness variation; and subtracting, using the at least one computing device, the fitting from the thickness variation to generate a residual structure for collecting a residual flatness measurement.

Abstract: A method of forming a semiconductor wafer includes generating a stress topography model of a semiconductor wafer with a plurality of desired structures in a desired layout. The method also includes determining a topography and calculating a compensation pattern based upon the topography, wherein the compensation pattern balances wafer topography. The method also includes patterning a semiconductor front side with the plurality of desired microstructures in the desired layout. The method also includes patterning the semiconductor back side with a compensation block mask corresponding to the compensation pattern.

Abstract: A method of forming a semiconductor wafer includes generating a stress topography model of a semiconductor wafer with a plurality of desired structures in a desired layout. The method also includes determining a topography and calculating a compensation pattern based upon the topography, wherein the compensation pattern balances wafer topography. The method also includes patterning a semiconductor front side with the plurality of desired microstructures in the desired layout. The method also includes patterning the semiconductor back side with a compensation block mask corresponding to the compensation pattern.

Abstract: Various embodiments include measurement structures and methods for measuring integrated circuit (IC) images. In some cases, a measurement structure for use in measuring an image of an IC, includes: a first section having a positive shift spacing pattern; a second section, on an opposite side of the measurement structure, having a negative shift spacing pattern; and a third section having a reference spacing pattern for calibrating a measurement from at least one of the first section or the second section.

Abstract: Various embodiments include measurement structures and methods for measuring integrated circuit (IC) images. In some cases, a measurement structure for use in measuring an image of an IC, includes: a first section having a positive shift spacing pattern; a second section, on an opposite side of the measurement structure, having a negative shift spacing pattern; and a third section having a reference spacing pattern for calibrating a measurement from at least one of the first section or the second section.

Abstract: A method for preventing buckling in a substrate using a tensile hard mask is provided. The method may include forming a mask over a substrate, the hard mask including a first area having a pattern for forming a plurality of openings and an adjacent second area free of openings, and the hard mask includes a tensile stress therein. The hard mask may be used to form the plurality of openings in the substrate. Partially eroding the hard mask leaves the substrate with the plurality of openings therein and a substantially planar surface, having diminished buckling.

Abstract: A method for preventing buckling in a substrate using a tensile hard mask is provided. The method may include forming a mask over a substrate, the hard mask including a first area having a pattern for forming a plurality of openings and an adjacent second area free of openings, and the hard mask includes a tensile stress therein. The hard mask may be used to form the plurality of openings in the substrate. Partially eroding the hard mask leaves the substrate with the plurality of openings therein and a substantially planar surface, having diminished buckling.

Abstract: A dose and focus monitor structure includes at least one complementary set of unit dose monitors and at least one complementary set of unit focus monitors. Each complementary set of unit dose monitors generate edges on a photoresist layer such that the edges move in opposite directions as a function of a dose offset. Each complementary set of unit focus monitors generates edges on the photoresist layer such that the edges move in opposite directions as a function of a focus offset. The dose and focus monitor structure generates self-compensating differential measurements of the dose offset and the focus offset such that the dose offset measurement and the focus offset measurement are independent of each other.

Abstract: A focus monitor structure on a reticle includes a lithographic feature region, a horizontal grating region including a horizontal grating located on one side of the lithographic feature region, and a vertical grating region including a vertical grating located on the opposite side of the lithographic feature region. A polarized illumination beam causes a printed image of the lithographic feature region to shift either toward the direction of the horizontal grating region or toward the direction of the vertical grating region in a manner that depends on the sign of the focus offset of the photoresist layer relative to the lens of an exposure tool. The magnitude and sign of the focus offset can be monitored to provide a real-time feedback on the focus offset of the exposure tool by measuring the shift of the printed image of the lithographic feature region.

Abstract: Deformation of a substrate due to one or more processing steps is determined by measuring substrate alignment data at lithographic processing steps before and after the one or more processing steps. Any abnormal pattern in the alignment data differential is identified by comparing the calculated alignment data differential with previous data accumulated in a database. By comparing the abnormal pattern with previously identified tool-specific patterns for alignment data differential, a processing step that introduces the abnormal pattern and/or the nature of the abnormal processing can be identified, and appropriate process control measures can be taken to rectify any anomaly in the identified processing step.

Abstract: A method includes selecting a mask blank for lithographically forming a desired pattern of main features to be printed onto a wafer by projection lithography. First locations are identified in the desired pattern, the first locations being those which would produce on the wafer images impacted by phase distortions of actinic light through openings in the desired pattern. Second locations in the desired pattern are identified for the insertion of orthoedges. The orthoedges are provided to contribute an additional amplitude of actinic light to the images impacted by phase distortions when the actinic light is projected onto the wafer. The orthoedges are then inserted into the desired pattern at the second locations at orientations such that the orthoedges provide a quadrature component to the additional amplitude of actinic light having an opposite sign to the quadrature component of the actinic light producing the phase distortions.

Abstract: A method includes selecting a mask blank for lithographically forming a desired pattern of main features to be printed onto a wafer by projection lithography. First locations are identified in the desired pattern, the first locations being those which would produce on the wafer images impacted by phase distortions of actinic light through openings in the desired pattern. Second locations in the desired pattern are identified for the insertion of orthoedges. The orthoedges are provided to contribute an additional amplitude of actinic light to the images impacted by phase distortions when the actinic light is projected onto the wafer. The orthoedges are then inserted into the desired pattern at the second locations at orientations such that the orthoedges provide a quadrature component to the additional amplitude of actinic light having an opposite sign to the quadrature component of the actinic light producing the phase distortions.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: A dose and focus monitor structure includes at least one complementary set of unit dose monitors and at least one complementary set of unit focus monitors. Each complementary set of unit dose monitors generate edges on a photoresist layer such that the edges move in opposite directions as a function of a dose offset. Each complementary set of unit focus monitors generates edges on the photoresist layer such that the edges move in opposite directions as a function of a focus offset. The dose and focus monitor structure generates self-compensating differential measurements of the dose offset and the focus offset such that the dose offset measurement and the focus offset measurement are independent of each other.

Abstract: This invention relates to the manufacture of semiconductor substrates such as wafers and to a method for monitoring the state of polarization incident on a photomask in projection printing using a specially designed polarization monitoring reticle for high numerical aperture lithographic scanners. The reticle measures 25 locations across the slit and is designed for numerical apertures above 0.85. The monitors provide a large polarization dependent signal which is more sensitive to polarization. A double exposure method is also provided using two reticles where the first reticle contains the polarization monitors, clear field reference regions and low dose alignment marks. The second reticle contains the standard alignment marks and labels. For a single exposure method, a tri-PSF low dose alignment mark is used. The reticles also provide for electromagnetic bias wherein each edge is biased depending on that edge's etch depth.

Abstract: A focus monitor structure on a reticle includes a lithographic feature region, a horizontal grating region including a horizontal grating located on one side of the lithographic feature region, and a vertical grating region including a vertical grating located on the opposite side of the lithographic feature region. A polarized illumination beam causes a printed image of the lithographic feature region to shift either toward the direction of the horizontal grating region or toward the direction of the vertical grating region in a manner that depends on the sign of the focus offset of the photoresist layer relative to the lens of an exposure tool. The magnitude and sign of the focus offset can be monitored to provide a real-time feedback on the focus offset of the exposure tool by measuring the shift of the printed image of the lithographic feature region.

Abstract: Methods, systems and apparatus for monitoring the state of a reticle by providing a reticle having a device exposure region in an imaging tool, defining one or more image fields across the device exposure region, and transmitting energy through the device exposure region. A detector detects the energy in the image field(s) at one or more testing intervals and a system control generates a transmission profile of average energy transmissions for each image field. Using this transmission profile, the state of the reticle is then determined at each testing interval followed by taking action based on the reticle state. The state of the reticle identifies whether the device exposure region has been deleteriously degraded, and as such, the reticle is no longer suitable for use. This is accomplished by determining if any average energy transmission of any image field across the reticle exceeds an allowable energy transmission threshold.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.