Abstract: An apparatus for dry hydro-therapy body massage of a user in a reclined position, including a housing structure having a user support surface for supporting the user in a seated position, the user support surface including a seat back portion, a seat portion with a semi-cylindrical main seat section and a leg seat section, wherein the seat back portion and the leg seat section are in relative angular relation to each other and the main seat section is disposed therebetween, and a fluid spray assembly interiorly within the housing structure for directing a fluid stream at the user support surface for imparting a massaging effect through the support surface to the upper body portion and lower body portion of the user.

Abstract: A bracket assembly includes a die struck metal plate, a molded plastic guide/nail set configured to fit over the die struck metal plate, the molded plastic guide/nail set including three spaced apart apertures, each of the apertures configured at an angle with respect to a central surface of the guide/nail set, the central surface comprising two upper opposing wings and a lower central wing configured to receive and secure an accessory, and common finish nails, the common finish nails used to secure the die struck metal plate and the molded plastic guide/nail set, when joined together, to a vertical surface.

Abstract: Various embodiments are generally directed to techniques for generating updating, and/or validating one or more aspects of an access policy for a data bucket, such as based on usage data corresponding to the data bucket, for instance. Some embodiments are particularly directed to automatically generating, updating, and/or validating an access policy for a data bucket based on analysis of log data corresponding to the data bucket. In some embodiments, log data comprising access records to a data bucket may be analyzed to determine access requirements for a set of entities. In some such embodiments, the access requirements for the set of entities may then be used to generate an access policy for the data bucket.

Abstract: Advertisers specify the size of an ad in pixels or in physical units such as inches or millimeters. The physical square area of an ad specified in pixels will change as the physical size of the television screen or computer display screen varies. The number of pixels of an ad specified in inches or millimeters will also change as the physical size of the television screen or computer display screen varies. The present invention manages the issue of keeping the physical area size of an image constant across television display screens regardless of the physical size of the screen.

Abstract: An exchange computer system may perform operations associated with cleared loan deliverable futures contracts. A holder of a long interest in a cleared loan deliverable futures contract may agree to pay a principle amount, at a designated future settlement time, in return for subsequent repayment of that amount with interest. A holder of a short interest in a cleared loan deliverable futures contract may agree to borrow the principle amount at the settlement time and to repay that amount, with interest, at the subsequent time.

Abstract: An apparatus having operand registers, an opcode detector, a carryless preformat unit, a compressor, a left shifter, and exclusive-OR logic. The operand registers receive operands for a carryless multiplication. The opcode detector receives a carryless multiplication instruction, and asserts a carryless signal. The carryless preformat unit partitions a first operand into a plurality of parts that are such that a Booth encoder is precluded from selection of second partial products of a second operand, where the second partial products reflect implicit carry operations. The compressor sums first partial products of the second operand via carry save adders arranged in a Wallace tree configuration, where generation of carry bits is disabled. The left shifter shifts one or more outputs of the compressor. The exclusive-OR logic executes an exclusive-OR function to yield a carryless multiplication result.

Abstract: An apparatus having a carryless preformat unit, a Booth encoder, a compressor, a left shifter, and exclusive-OR logic. The carryless preformat unit receives a multiplier operand and partitions the multiplier operand into parts. The Booth encoder receives the parts and directs selection of first partial products of a multiplicand that do not reflect implicit carry operations. The compressor sums the first partial products via a configuration of carry save adders that generate sum bits and carry bits, where generation of the carry bits is disabled during execution of the carryless multiplication. The left shifter shifts bits of one or more outputs of the compressor. The exclusive-OR logic is coupled to the compressor and the left shifter, and is configured to execute an exclusive-OR function on the outputs to yield a carryless multiplication result.

Abstract: An apparatus is provided for performing carryless multiplication. The apparatus has an opcode dectector and a carryless preformat unit. The opcode dectector is configured to receive a carryless multiplication instruction, and is configured to assert a carryless signal responsive to receipt of the carryless multiplication instruction. The carryless preformat unit is configured to partition the first operand into parts responsive to assertion of the carryless signal, where the parts are configured such that a Booth encoder selects first partial products corresponding to a second operand and is precluded from selection of second partial products corresponding to the second operand, and where the second partial products are results of implicit carry operations. The first partial products are exclusive-ORed together to yield a carryless multiplication result.

Abstract: A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions to the execution units and selects sources of the instruction operands. At least one of the execution units detects one of the operands of one of the instructions is a denormal operand, generates an indication that the instruction needs to be replayed in response to detecting the denormal operand, and provides the denormal operand to the instruction scheduler in response to detecting the denormal operand, rather than normalizing the denormal operand. The instruction scheduler normalizes the denormal operand, in response to the indication, and causes the normalized operand, rather than the denormal operand, to be provided to the execution unit when the instruction is replayed.

Abstract: Scroll wheels have simplified the movement of cursors and changes in focus as a users navigate their way through menus, lists, tables, and other objects typically found in graphical user interfaces. Also typical of navigation schemes driven by scroll wheels is the ability of the user to accelerate the rate of movement of the cursor or focus by spinning the scroll wheel faster. One issue with this behavior is that a user who over accelerates the scroll wheel will often wind up overshooting his intended target and reversing the direction of the scroll wheel several times. The embodiment addresses this problem by giving control of the speed of the cursor or focus movement to the object being navigated. If the granularity of the list, table, menu, or other objects become smaller, the object has the ability to filter the speed input of the scroll wheel.

Abstract: An apparatus is provided for performing carryless multiplication. The apparatus has an opcode dectector and a carryless preformat unit. The opcode dectector is configured to receive a carryless multiplication instruction, and is configured to assert a carryless signal responsive to receipt of the carryless multiplication instruction. The carryless preformat unit is configured to partition the first operand into parts responsive to assertion of the carryless signal, where the parts are configured such that a Booth encoder selects first partial products corresponding to a second operand and is precluded from selection of second partial products corresponding to the second operand, and where the second partial products are results of implicit carry operations. The first partial products are exclusive-ORed together to yield a carryless multiplication result.

Abstract: An apparatus having operand registers, an opcode dectector, a carryless preformat unit, a compressor, a left shifter, and exclusive-OR logic. The operand registers receive operands for a carryless multiplication. The opcode dectector receives a carryless multiplication instruction, and asserts a carryless signal. The carryless preformat unit partitions a first operand into a plurality of parts that are such that a Booth encoder is precluded from selection of second partial products of a second operand, where the second partial products reflect implicit carry operations. The compressor sums first partial products of the second operand via carry save adders arranged in a Wallace tree configuration, where generation of carry bits is disabled. The left shifter shifts one or more outputs of the compressor. The exclusive-OR logic executes an exclusive-OR function to yield a carryless multiplication result.

Abstract: An apparatus having a carryless preformat unit, a Booth encoder, a compressor, a left shifter, and exclusive-OR logic. The carryless preformat unit receives a multiplier operand and partitions the multiplier operand into parts. The Booth encoder receives the parts and directs selection of first partial products of a multiplicand that do not reflect implicit carry operations. The compressor sums the first partial products via a configuration of carry save adders that generate sum bits and carry bits, where generation of the carry bits is disabled during execution of the carryless multiplication. The left shifter shifts bits of one or more outputs of the compressor. The exclusive-OR logic is coupled to the compressor and the left shifter, and is configured to execute an exclusive-OR function on the outputs to yield a carryless multiplication result.

Abstract: Pharmaceutical and/or veterinary formulation containing about 2-30% (w/w) (on an active basis) of at least one active agent, about 0.5-20.0% (w/w) of a pore-forming agent comprising lecithin and an organic salt, and the balance stearin.

Abstract: An x87 fused multiply-add (FMA) instruction in the instruction set of an x86 architecture microprocessor is disclosed. The FMA instruction implicitly specifies the two factor operands as the top two operands of the x87 FPU register stack and explicitly specifies the third addend operand as a third x87 FPU register stack register. The microprocessor multiplies the first two operands and adds the product to the third operand to generate a result. The result is stored into the third register and the first two operands are popped off the stack. In an alternate embodiment, the third operand is also implicitly specified as being stored in the register that is two registers below the top of stack register; the result is also stored therein. The instruction opcode value is in the x87 opcode range.