Abstract: An opt-out actuator for which actuation is cancelled if the operator changes his or her state within a prescribed amount of time. The operator is informed of “entering” the conditions for actuation by a first sensory means. After an optional grace period to lower the incidence of accidentally and temporarily meeting these conditions, the operator is informed of the “cocking” of the actuator by a second sensory means. The operator then has a longer period in which to opt-out of the actuator by changing his or her state. If the operator does not opt out by changing state, the actuator fires and the operator is informed by a third sensory means. If the operator opts out, the operator is informed of this “canceling” by a fourth sensory means which could be the reversion of continuous sensory feedback to its state prior to the triggering of the actuator and which serves as confirmation to the operator that actuation has been cancelled.

Abstract: In this method for viewing multiple images (or movies), the images can be thought of as being piled up and a grid of tiles is placed on top. Each tile functions like a window onto one of the images. One or more view screens are placed over some of the tiles, and one or more input devices are provided. Cursors are moved around the view screens and over the tiles. When a cursor remains within the borders of one of the tiles for longer than a predetermined amount of time, the image displayed in the tile changes. Should the user click the tile, a “spreading” process is initiated whereby the number of tiles displaying the image clicked on begins to increase. Pressing a keyboard button causes the same spreading to be initiated beneath the cursor but with the image associated with that button rather than the one in the tile beneath the cursor.

Abstract: An apparatus and method for bi-directional format conversion and transfer of data between integer and floating point registers is provided. A floating point register is configured to store floating point data, and integer data, in a variety of numerical formats. Data is moved in and out of the floating point register as integer data, and is converted into floating point format as needed. Separate processor instructions are provided for format conversion and data transfer to allow conversion and transfer operations to be separated.

Abstract: An apparatus and method for bi-directional format conversion and transfer of data between integer and floating point registers is provided. A floating point register is configured to store floating point data, and integer data, in a variety of numerical formats. Data is moved in and out of the floating point register as integer data, and is converted into floating point format as needed. Separate processor instructions are provided for format conversion and data transfer to allow conversion and transfer operations to be separated.

Abstract: An apparatus and method for bi-directional format conversion and transfer of data between integer and floating point registers is provided. A floating point register is configured to store floating point data, and integer data, in a variety of numerical formats. Data is moved in and out of the floating point register as integer data, and is converted into floating point format as needed. Separate processor instructions are provided for format conversion and data transfer to allow conversion and transfer operations to be separated.

Abstract: An apparatus and method for bi-directional format conversion and transfer of data between integer and floating point registers is provided. A floating point register is configured to store floating point data, and integer data, in a variety of numerical formats. Data is moved in and out of the floating point register as integer data, and is converted into floating point format as needed. Separate processor instructions are provided for format conversion and data transfer to allow conversion and transfer operations to be separated.

Abstract: An apparatus and method are provided for concurrently loading single-precision operands into registers in a microprocessor floating point register file. The apparatus includes translation logic, data logic, and write back logic. The translation logic receives a load macro instruction prescribing an address, and decodes the load macro instruction into a double load micro instruction. The double load micro instruction directs the microprocessor to retrieve the two single-precision operands from the address and to load the two single-precision operands into the two floating point registers. The data logic, coupled to the translation logic, executes the double load micro instruction and retrieves the two single-precision operands from the address. The write back logic, coupled to the data logic, loads the two single-precision operands into the two floating point registers during a single write cycle.

Abstract: An apparatus and method for performing single precision multiplication in a microprocessor are provided. The apparatus includes translation logic and extended precision floating point execution logic. The translation logic decodes a single precision multiply instruction into an associated micro instruction sequence directing the microprocessor to fetch a single precision operand from memory and convert it to extended precision format. In addition, the associated micro instruction sequence directs floating point execution logic employing a dual pass multiplication unit to skip a pass associated with computing an insignificant partial product. This insignificant partial product would otherwise result from multiplication of a multiplicand by zeros which are appended to the significand of the fetched operand when it is converted to extended precision format.

Abstract: An apparatus and method for calculating a square root of an operand in a microprocessor are provided. The microprocessor has a plurality of square root instructions, each of which specifies a square root calculation precision. The apparatus includes translation logic and execution logic. The translation logic decodes the square root macro instruction into a plurality of prescribed-precision machine instructions according to the square root calculation precision specified by the plurality of square root instructions. The execution logic, coupled to the translation logic, receives the plurality of prescribed-precision machine instructions and calculates the square root of the operand according to the specified square root calculation precision. At least one of the plurality of square root instructions specifies the square root calculation precision such that less significant bits are calculated in the square root than are provided in the operand.

Abstract: A disk drive with a disk having a servo pattern including a special "calibration track" wherein a plurality of calibration burst pairs are recorded on a spiral centerline to define null points that are radially shifted from a burst pair centerline by precise, predefined or subsequently measured, fractional track amounts to collectively provide accurate information about servo signal values generated as a function of real displacement. The calibration burst pairs beneficially allow for calibrating the PES signal after the drive is removed from the servowriter during a manufacturing phase called Intelligent Burn-In. The calibration bursts are recorded on a spiral to reduce the recording time and are preferably written in data regions so that they are disposable and may be selectively written over with data to maximize storage space. Some or all of the calibration burst pairs may be retained for a subsequent recalibration.

Abstract: An apparatus and method for performing a floating point multiply (by a fixed graphics constant), and converting the product of the multiply into an integer, within a single operation is provided. The apparatus includes detection logic to determine whether a special multiply/convert operation is specified, and if so, floating point conversion logic to adjust a bias constant prior to conversion of the floating point number to an integer. More specifically, if the multiply/convert operation specified relates to calculation of graphic points for display, execution of the multiply convert operation effectively multiplies a specified floating point number by a graphics constant, as part of subtracting the exponent bias.

Abstract: A microprocessor is provided for executing a floating point exchange micro instruction sequence to swap the contents a first location and a second location. The microprocessor includes register/control logic that receives a floating point micro instruction, determines that the contents of the first location depend upon resolution of a preceding floating point micro instruction, and provides a signal indicating the dependency. The microprocessor also has interlock logic that, in the event of a dependency forwards a new target location to the preceding floating point micro instruction. The microprocessor also includes target location modification logic that receives the new target location and for provides the new target location to the preceding floating point micro instruction. Modification of the target location allows the floating point exchange micro instruction sequence to execute without resolution delay.

Abstract: The invention relates generally to rotating magnetic storage disk drive and, more particularly, to a method of seamlessly recording circumferentially overlapping servo bursts on a magnetic disk with successive passes of a write head that is guided by a servo track writer wherein the servo bursts are contained in at least two servo burst groups that each have at least one circumferential burst position which may contain a servo burst.

Abstract: An apparatus for handling special cases outside of normal floating-point arithmetic functions is provided that is used in a floating-point unit used for calculating arithmetic functions. The floating-point unit generates an exponent portion and a mantissa portion and a writeback stage is coupled to the exponent portion and to the mantissa portion and is specifically used to handle the special cases outside the normal float arithmetic functions. A spill stage is also provided and is coupled to the writeback stage to receive a resultant exponent and mantissa. A register file unit is coupled to the writeback stage and the spill stage through a plurality of rename busses, which are used to carry results between the writeback stage and spill stage and the register file. The spill stage is serially coupled to the writeback stage so as to provide a smooth operation in the transition of operating on the results from the writeback stage for the exponent and mantissa.

Abstract: A processing system that determines whether an underflow or overflow condition has occurred concurrently with the determination of the floating point exponent result uses a group of latched constants which can be added to the intermediate exponent and the exponent adjust to determine out of range conditions for all cases. The appropriate one of these latched constants (exponent range check values; exp.sub.-- range.sub.-- chk) are added to the exp.sub.-- int and exp.sub.-- adjust to give a value that will vary based on whether the exp.sub.-- result is out of range, or not. Different exp.sub.-- range.sub.-- chk values are used for underflow single precision, underflow double precision, overflow single precision and overflow double precision. The sum of these three values (exp.sub.-- int, exp.sub.-- adj, exp.sub.-- range.sub.-- chk) will yield a binary number having a most significant bit (MSB) that is dependent upon the exp.sub.-- result value.

Abstract: A result normalizer (58) for use with an adder (56) generates a mask in two stages that indicates the location of the leading one in the adder result. In the first stage, a leading zero anticipator (68) determines the position to within two digits. In the second stage, a count leading zero indicator (70) determines the position to a single digit. The mask is used to control the number of digits that each stage of a multiplexer array (66) shifts the adder result. The output of the multiplexer array thereby contains a leading one. The result normalizer may be advantageously used in high performance applications such as in a floating point execution unit in a data processor or in digital signal processing systems.