Patents by Inventor Timothy B. Cowles

Timothy B. Cowles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10643672
    Abstract: A memory device is provided. The memory device comprises a memory array and circuitry configured to determine one or more settings for the memory array corresponding to a powered-on state of the memory device, to store the one or more settings in a non-volatile memory location, and in response to returning to the powered-on state from a reduced-power state, to read the one or more settings from the non-volatile memory location.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan S. Parry, George B. Raad, James S. Rehmeyer, Timothy B. Cowles
  • Patent number: 10643717
    Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan S. Parry, George B. Raad, James S. Rehmeyer, Timothy B. Cowles
  • Publication number: 20200111525
    Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.
    Type: Application
    Filed: October 9, 2019
    Publication date: April 9, 2020
    Inventors: Timothy B. Cowles, Dean D. Gans, Jiyun Li, Nathaniel J. Meier, Randall J. Rooney
  • Patent number: 10606743
    Abstract: The present disclosure includes apparatuses and methods related to data movement operations in non-volatile memory. An example apparatus can comprise an array of non-volatile memory cells including a plurality of sections each with a plurality of rows and a controller configured to move data stored in a first portion of the array from a first row of a first section to a second row of the first section and move data stored in a second portion of the array from a second section to the first to create an open row in the second section in response to data from a particular number of portions of memory cells in the first section being moved within the first section.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: James S. Rehmeyer, Timothy B. Cowles
  • Publication number: 20200035309
    Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.
    Type: Application
    Filed: October 2, 2019
    Publication date: January 30, 2020
    Inventors: Jonathan S. Parry, George B. Raad, James S. Rehmeyer, Timothy B. Cowles
  • Patent number: 10541017
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: January 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: George B. Raad, Jonathan S. Parry, James S. Rehmeyer, Timothy B. Cowles
  • Publication number: 20190371420
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.
    Type: Application
    Filed: August 17, 2019
    Publication date: December 5, 2019
    Inventors: Timothy B. Cowles, George B. Raad, James S. Rehmeyer, Jonathan S. Parry
  • Publication number: 20190371392
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 5, 2019
    Inventors: George B. Raad, Jonathan S. Parry, James S. Rehmeyer, Timothy B. Cowles
  • Patent number: 10482945
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: George B. Raad, Jonathan S. Parry, James S. Rehmeyer, Timothy B. Cowles
  • Patent number: 10475519
    Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: November 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan S. Parry, George B. Raad, James S. Rehmeyer, Timothy B. Cowles
  • Publication number: 20190325966
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Inventors: Timothy B. Cowles, George B. Raad, James S. Rehmeyer, Jonathan S. Parry
  • Publication number: 20190325974
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Inventors: Timothy B. Cowles, George B. Raad, James S. Rehmeyer, Jonathan S. Parry
  • Patent number: 10446248
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Timothy B. Cowles, George B. Raad, James S. Rehmeyer, Jonathan S. Parry
  • Publication number: 20190295606
    Abstract: A memory device is provided. The memory device comprises a memory array and circuitry configured to determine one or more settings for the memory array corresponding to a powered-on state of the memory device, to store the one or more settings in a non-volatile memory location, and in response to returning to the powered-on state from a reduced-power state, to read the one or more settings from the non-volatile memory location.
    Type: Application
    Filed: March 23, 2018
    Publication date: September 26, 2019
    Inventors: Jonathan S. Parry, George B. Raad, James S. Rehmeyer, Timothy B. Cowles
  • Publication number: 20190295666
    Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.
    Type: Application
    Filed: March 23, 2018
    Publication date: September 26, 2019
    Inventors: Jonathan S. Parry, George B. Raad, James S. Rehmeyer, Timothy B. Cowles
  • Patent number: 10424365
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: George B. Raad, Jonathan S. Parry, James S. Rehmeyer, Timothy B. Cowles
  • Publication number: 20190228817
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
    Type: Application
    Filed: April 4, 2019
    Publication date: July 25, 2019
    Inventors: George B. Raad, Jonathan S. Parry, James S. Rehmeyer, Timothy B. Cowles
  • Publication number: 20190228816
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
    Type: Application
    Filed: April 4, 2019
    Publication date: July 25, 2019
    Inventors: George B. Raad, Jonathan S. Parry, James S. Rehmeyer, Timothy B. Cowles
  • Publication number: 20190171558
    Abstract: The present disclosure includes apparatuses and methods related to data movement operations in non-volatile memory. An example apparatus can comprise an array of non-volatile memory cells including a plurality of sections each with a plurality of rows and a controller configured to move data stored in a first portion of the array from a first row of a first section to a second row of the first section and move data stored in a second portion of the array from a second section to the first to create an open row in the second section in response to data from a particular number of portions of memory cells in the first section being moved within the first section.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 6, 2019
    Inventors: James S. Rehmeyer, Timothy B. Cowles
  • Patent number: 10297309
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: May 21, 2019
    Assignee: Micron Technology, Inc.
    Inventors: George B. Raad, Jonathan S. Parry, James S. Rehmeyer, Timothy B. Cowles