Patents by Inventor Timothy Dooling Sullivan
Timothy Dooling Sullivan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9404953Abstract: Embodiments of the present invention provide a variety of structures and method for detecting abnormalities in the back-end-of-line (BEOL) stack and BEOL structures located in close proximity to through-silicon vias (TSVs) in a 3D integrated chip. The detected abnormalities may include stress, strain, and damage that will affect metallization continuity, interfacial integrity within a metal level, proximity accuracy of the TSV placement, and interlevel dielectric integrity and metallization-to-TSV dielectric integrity. Additionally, these structures in conjunction with each other are capable of determining the range of influence of the TSV. That is, how close to the TSV that a BEOL line (or via) needs to be in order to be influenced by the TSV.Type: GrantFiled: October 31, 2013Date of Patent: August 2, 2016Assignee: International Business Machines CorporationInventors: Fen Chen, Mukta G. Farooq, John A. Griesemer, Chandrasekharan Kothandaraman, John Matthew Safran, Timothy Dooling Sullivan
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Patent number: 9105465Abstract: The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.Type: GrantFiled: March 22, 2011Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Timothy Harrison Daubenspeck, Jeffrey P. Gambino, Christopher David Muzzy, Wolfgang Sauter, Timothy Dooling Sullivan
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Publication number: 20150115982Abstract: Embodiments of the present invention provide a variety of structures and method for detecting abnormalities in the back-end-of-line (BEOL) stack and BEOL structures located in close proximity to through-silicon vias (TSVs) in a 3D integrated chip. The detected abnormalities may include stress, strain, and damage that will affect metallization continuity, interfacial integrity within a metal level, proximity accuracy of the TSV placement, and interlevel dielectric integrity and metallization-to-TSV dielectric integrity. Additionally, these structures in conjunction with each other are capable of determining the range of influence of the TSV. That is, how close to the TSV that a BEOL line (or via) needs to be in order to be influenced by the TSV.Type: ApplicationFiled: October 31, 2013Publication date: April 30, 2015Applicant: International Business Machines CorporationInventors: Fen Chen, Mukta G. Farooq, John A. Griesemer, Chandrasekharan Kothandaraman, John Matthew Safran, Timothy Dooling Sullivan
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Patent number: 8945955Abstract: A method for changing reflectance or resistance of a region in an optoelectronic memory device. Changing the reflectance of the region includes sending an electric current through the region to cause a reflectance change in the region. Changing the resistance of the region includes: projecting a laser beam at a first beam intensity on the region, resulting in the region changing from a first to a second different resistance value; electrically reading the second resistance value during which an optical signal carried by the laser beam has a first digital value; after electrically reading the second resistance value, the laser beam is projected at a second beam intensity on the region resulting in the region changing from the second to the first resistance value; and electrically reading the first resistance value of the region while the laser beam is being projected on the region at the second beam intensity.Type: GrantFiled: February 13, 2013Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Fen Chen, Richard Steven Kontra, Tom C. Lee, Theodore M. Levin, Christopher David Muzzy, Timothy Dooling Sullivan
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Patent number: 8592976Abstract: A structure. The structure includes: a first dielectric layer which includes a top dielectric surface; an electrically conductive line on the first dielectric layer; a second dielectric layer on the first dielectric layer and the electrically conductive line; a ball-limiting-metallurgy (BLM) region on the second dielectric layer and the electrically conductive line such that the BLM region is electrically connected to the electrically conductive line; and a solder ball on the BLM region. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface and is entirely in the BLM region does not exceed a pre-specified maximum value, wherein the pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface.Type: GrantFiled: September 14, 2012Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Timothy Harrison Daubenspeck, Wolfgang Sauter, Timothy Dooling Sullivan
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Publication number: 20130258765Abstract: A method for changing reflectance or resistance of a region in an optoelectronic memory device. Changing the reflectance of the region includes sending an electric current through the region to cause a reflectance change in the region. Changing the resistance of the region includes: projecting a laser beam at a first beam intensity on the region, resulting in the region changing from a first to a second different resistance value; electrically reading the second resistance value during which an optical signal carried by the laser beam has a first digital value; after electrically reading the second resistance value, the laser beam is projected at a second beam intensity on the region resulting in the region changing from the second to the first resistance value; and electrically reading the first resistance value of the region while the laser beam is being projected on the region at the second beam intensity.Type: ApplicationFiled: February 13, 2013Publication date: October 3, 2013Applicant: International Business Machines CorporationInventors: Fen Chen, Richard Steven Kontra, Tom C. Lee, Theodore M. Levin, Christopher David Muzzy, Timothy Dooling Sullivan
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Publication number: 20130008699Abstract: A structure. The structure includes: a first dielectric layer which includes a top dielectric surface; an electrically conductive line on the first dielectric layer; a second dielectric layer on the first dielectric layer and the electrically conductive line; a ball-limiting-metallurgy (BLM) region on the second dielectric layer and the electrically conductive line such that the BLM region is electrically connected to the electrically conductive line; and a solder ball on the BLM region. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface and is entirely in the BLM region does not exceed a pre-specified maximum value, wherein the pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: International Business Machines CorporationInventors: Charles L. Arvin, Timothy Harrison Daubenspeck, Wolfgang Sauter, Timothy Dooling Sullivan
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Publication number: 20120287707Abstract: A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.Type: ApplicationFiled: July 26, 2012Publication date: November 15, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fen Chen, Richard Steven Kontra, Tom C. Lee, Theodore M. Levin, Christopher David Muzzy, Timothy Dooling Sullivan
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Patent number: 8299611Abstract: A solder ball structure and a method for forming the same. The structure includes (i) a first dielectric layer which includes a top dielectric surface, (ii) an electrically conductive line, (iii) a second dielectric layer, (iv) a ball-limiting-metallurgy (BLM) region, and (v) a solder ball. The BLM region is electrically connected to the electrically conductive line and the solder ball. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface of the first dielectric layer and is entirely in the BLM region does not exceed a pre-specified maximum value. The pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface of the first dielectric layer.Type: GrantFiled: August 26, 2009Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Timothy Harrison Daubenspeck, Wolfgang Sauter, Timothy Dooling Sullivan
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Patent number: 8288747Abstract: A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.Type: GrantFiled: July 23, 2010Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Fen Chen, Richard Steven Kontra, Tom C. Lee, Theodore M. Levin, Christopher David Muzzy, Timothy Dooling Sullivan
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Patent number: 8288270Abstract: The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.Type: GrantFiled: February 15, 2012Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Mukta G Farooq, John A Griesemer, Gary LaFontant, William Francis Landers, Timothy Dooling Sullivan
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Publication number: 20120241916Abstract: The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.Type: ApplicationFiled: March 22, 2011Publication date: September 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Harrison Daubenspeck, Jeffrey P. Gambino, Christopher David Muzzy, Wolfgang Sauter, Timothy Dooling Sullivan
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Publication number: 20120199975Abstract: The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.Type: ApplicationFiled: February 9, 2011Publication date: August 9, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, John A. Griesemer, Gary LaFontant, William Francis Landers, Timothy Dooling Sullivan
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Publication number: 20120199983Abstract: The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.Type: ApplicationFiled: February 15, 2012Publication date: August 9, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, John A. Griesemer, Gary LaFontant, William Francis Landers, Timothy Dooling Sullivan
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Patent number: 8237288Abstract: The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.Type: GrantFiled: February 9, 2011Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Mukta G Farooq, John A Griesemer, Gary LaFontant, William Francis Landers, Timothy Dooling Sullivan
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Patent number: 8207609Abstract: A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.Type: GrantFiled: August 1, 2011Date of Patent: June 26, 2012Assignee: International Business Machines CorporationInventors: Stephen Peter Ayotte, Jeffrey Peter Gambino, Timothy Dooling Sullivan, Kimball M. Watson
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Patent number: 8110875Abstract: A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.Type: GrantFiled: July 2, 2008Date of Patent: February 7, 2012Assignee: International Business Machines CorporationInventors: John Joseph Ellis-Monaghan, Jeffrey Peter Gambino, Timothy Dooling Sullivan, Steven Howard Voldman
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Publication number: 20110284280Abstract: A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.Type: ApplicationFiled: August 1, 2011Publication date: November 24, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Peter Ayotte, Jeffrey Peter Gambino, Timothy Dooling Sullivan, Kimball M. Watson
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Patent number: 8017514Abstract: A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.Type: GrantFiled: May 5, 2008Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Stephen Peter Ayotte, Jeffrey Peter Gambino, Timothy Dooling Sullivan, Kimball M. Watson
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Patent number: 7861204Abstract: A design structure including an integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction.Type: GrantFiled: December 20, 2007Date of Patent: December 28, 2010Assignee: International Business Machines CorporationInventors: Anthony Kendall Stamper, Timothy Dooling Sullivan, Ping-Chuan Wang