Abstract: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.

Abstract: A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.

Abstract: A solder ball structure and a method for forming the same. The structure includes (i) a first dielectric layer which includes a top dielectric surface, (ii) an electrically conductive line, (iii) a second dielectric layer, (iv) a ball-limiting-metallurgy (BLM) region, and (v) a solder ball. The BLM region is electrically connected to the electrically conductive line and the solder ball. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface of the first dielectric layer and is entirely in the BLM region does not exceed a pre-specified maximum value. The pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface of the first dielectric layer.

Abstract: A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.

Abstract: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.

Abstract: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.

Abstract: An integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction.

Abstract: A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.

Abstract: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.

Abstract: A design structure including an integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction.

Abstract: A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.

Abstract: A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.

Abstract: An integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction.

Abstract: A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection.

Abstract: A gap conducting structure for an integrated electronic circuit that functions as an electronic fuse device and that is integrated as part of the semi-conductor chip wiring for providing over-current and thermal runaway protection. The gap conducting structure includes one or more air gap regions of predefined volume that fully or partially exposes a length of interlevel conductor layer in an IC. Alternately, the air gap region may wholly located within the dielectric region below a corresponding conductor and separated by insulator. When functioning as a fuse, the gap region acts to reduce thermal conductivity away from the exposed portion of the conductor enabling generation of higher heat currents in the conducting line with lower applied voltages sufficient to destruct a part of the partially exposed/fully exposed conducting line, thus preventing thermal runaway and over-current condition.

Abstract: A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection.

Abstract: An improved process for depositing a conductive thin film upon an integrated circuit substrate by collimated sputtering is disclosed. The sputtered films are alloys of aluminum; a preferred alloying metal is magnesium. The sputtered films of the invention have a more uniform orientation of grains than sputtered aluminum copper silicon alloy films. Such processes are especially useful in the fabrication of integrated circuit devices having aluminum alloy wiring elements.