Patents by Inventor Timothy J. Dell
Timothy J. Dell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150270018Abstract: According to embodiments of the disclosure, methods, systems, and computer program products for memory module testing are disclosed. The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the plurality of memory modules including a first module having a first memory characteristic and a second module having a second memory characteristic. The method may include determining for the first module, a first traffic-to-temperature parameter, and determining that the first module was sufficiently stressed in response to determining that the first traffic-to-temperature parameter is within a first traffic-to-temperature range. The method may also include determining, for the second module, a second traffic-to-temperature parameter, and determining that the second module was sufficiently stressed in response to determining that the second traffic-to-temperature parameter is within a second traffic-to-temperature range.Type: ApplicationFiled: December 29, 2014Publication date: September 24, 2015Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Timothy J. Dell, Joab D. Henderson, Anil B. Lingambudi, Michael D. Pardeik
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Publication number: 20150205730Abstract: A method, system and memory controller for implementing enhanced security in a memory subsystem including DRAM in a computer system. A memory includes a register to hold scrambling information transmitted from a memory controller; and scrambling circuitry on the memory to scramble at least one of bank select bits and data bits responsive to the scrambling information in the register.Type: ApplicationFiled: January 20, 2014Publication date: July 23, 2015Applicant: International Business Machines CorporationInventors: Timothy J. Dell, Prasanna Jayaraman, Girisankar Paulraj, Diyanesh Babu C. Vidyapoornachary
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Publication number: 20150205731Abstract: A method, system and memory controller for implementing enhanced security in a memory subsystem including DRAM in a computer system. A memory includes a register to hold scrambling information transmitted from a memory controller; and scrambling circuitry on the memory to scramble at least one of bank select bits and data bits responsive to the scrambling information in the register.Type: ApplicationFiled: June 16, 2014Publication date: July 23, 2015Inventors: Timothy J. Dell, Prasanna Jayaraman, Girisankar Paulraj, Diyanesh Babu C. Vidyapoornachary
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Patent number: 9087615Abstract: A method for testing and correcting a memory system is described. The method includes selecting a target memory unit of the memory system having a timing margin in response to a trigger to start a timing margin measurement. The stored data in the target memory unit is moved to a spare memory unit. The memory system performs reads and writes of user data from the spare memory unit while measuring the target memory unit. The timing margins of the target memory unit are measured. The reliability of the measured timing margins of the target memory unit based on a timing margin profile is determined.Type: GrantFiled: May 3, 2013Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Anil B. Lingambudi, Diyanesh B. Vidyapoornachary
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Publication number: 20150178147Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.Type: ApplicationFiled: February 17, 2015Publication date: June 25, 2015Inventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
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Publication number: 20150169445Abstract: The present disclosure includes identifying, in a memory system, a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory; determining a memory segment size from the capacities of the memory modules; identifying a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and creating a virtual group that includes the first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.Type: ApplicationFiled: December 12, 2013Publication date: June 18, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy J. Dell, Prasanna Jayaraman, Anil B. Lingambudi, Girisankar Paulraj
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Publication number: 20150169446Abstract: The present disclosure includes identifying, in a memory system, a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory; determining a memory segment size from the capacities of the memory modules; identifying a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and creating a virtual group that includes the first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.Type: ApplicationFiled: April 8, 2014Publication date: June 18, 2015Applicant: International Business Machines CorporationInventors: Timothy J. Dell, Prasanna Jayaraman, Anil B. Lingambudi, Girisankar Paulraj
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Patent number: 9043569Abstract: A method and computer-readable storage media are provided for rearranging data in physical memory units. In one embodiment, a method may include monitoring utilization counters. The method may further include, comparing the utilization counters for a match with an instance in a first table containing one or more instances when data may be rearranged in the physical memory units. The table may further include where the data should be relocated by a rearrangement. The method may also include, continuing to monitor the utilization counters if a match is not found with an instance in the first table. The method may further include, rearranging the data in the physical memory units if a match between the utilization counters and an instance in the first table is found.Type: GrantFiled: May 31, 2013Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Timothy J. Dell, Manoj Dusanapudi, Prasanna Jayaraman, Anil B. Lingambudi
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Patent number: 9015522Abstract: A method, system and computer program product are provided for implementing dynamic random access memory (DRAM) failure scenarios mitigation using buffer techniques delaying usage of RAS features in computer systems. A buffer is provided with a memory controller. Physical address data read/write failures are analyzed. Responsive to identifying predefined failure types for physical address data read/write failures, the buffer is used to selectively store and retrieve data.Type: GrantFiled: December 4, 2012Date of Patent: April 21, 2015Assignee: International Business Machines CorporationInventors: Timothy J. Dell, Manoj Dusanapudi, Prasanna Jayaraman, Anil B. Lingambudi
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Patent number: 8996953Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment detects that a specified number of correctable errors is exceeded. In another step, an exemplary embodiment detects the occurrence of an uncorrectable error. In another step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.Type: GrantFiled: March 1, 2013Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
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Patent number: 8996935Abstract: A method and apparatus for operation of a memory module for storage of a data word is provided. The apparatus includes a memory module having a set of paired memory devices including a first memory device to store a first section of a data word and a second memory device to store a second section of the data word when used in failure free operation. The apparatus may further include a first logic module to perform a write operation by writing the first and second sections of the data word to both the first memory device and the second memory device upon the determination of certain types of failure. The determination may include that a failure exists in the word section storage of either the first or second memory devices but that no failures exist in equivalent locations of word section storage in the two memory devices.Type: GrantFiled: December 7, 2012Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Girisankar Paulraj, Saravanan Sethuraman
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Patent number: 8964495Abstract: A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.Type: GrantFiled: August 19, 2014Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Girisankar Paulraj, Saravanan Sethuraman
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Publication number: 20140355369Abstract: A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.Type: ApplicationFiled: August 19, 2014Publication date: December 4, 2014Inventors: Edgar R. Cordero, Timothy J. Dell, Girisankar Paulraj, Saravanan Sethuraman
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Publication number: 20140359241Abstract: A method and computer-readable storage media are provided for rearranging data in physical memory units. In one embodiment, a method may include monitoring utilization counters. The method may further include, comparing the utilization counters for a match with an instance in a first table containing one or more instances when data may be rearranged in the physical memory units. The table may further include where the data should be relocated by a rearrangement. The method may also include, continuing to monitor the utilization counters if a match is not found with an instance in the first table. The method may further include, rearranging the data in the physical memory units if a match between the utilization counters and an instance in the first table is found.Type: ApplicationFiled: May 31, 2013Publication date: December 4, 2014Inventors: Timothy J. Dell, Manoj Dusanapudi, Prasanna Jayaraman, Anil B. Lingambudi
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Publication number: 20140317473Abstract: A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.Type: ApplicationFiled: April 22, 2013Publication date: October 23, 2014Applicant: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
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Patent number: 8848470Abstract: A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.Type: GrantFiled: August 29, 2012Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Girisankar Paulraj, Saravanan Sethuraman
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Publication number: 20140250340Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment detects that a specified number of correctable errors is exceeded. In another step, an exemplary embodiment detects the occurrence of an uncorrectable error. In another step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.Type: ApplicationFiled: March 1, 2013Publication date: September 4, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
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Publication number: 20140157044Abstract: A method, system and computer program product are provided for implementing dynamic random access memory (DRAM) failure scenarios mitigation using buffer techniques delaying usage of RAS features in computer systems. A buffer is provided with a memory controller. Physical address data read/write failures are analyzed. Responsive to identifying predefined failure types for physical address data read/write failures, the buffer is used to selectively store and retrieve data.Type: ApplicationFiled: December 4, 2012Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy J. Dell, Manoj Dusanapudi, Prasanna Jayaraman, Anil B. Lingambudi
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Publication number: 20140063987Abstract: A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.Type: ApplicationFiled: August 29, 2012Publication date: March 6, 2014Applicant: International Business MachinesInventors: Edgar R. Cordero, Timothy J. Dell, Girisankar Paulraj, Saravanan Sethuraman
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Publication number: 20140025223Abstract: An approach is provided in which a subsystem cooling manager detects an increased workload indicator corresponding to a computer subsystem's forthcoming workload requirement. The forthcoming workload requirement corresponds to future computing resources required by the subsystem to support one or more software programs executing on the computer system. The subsystem cooling manager determines that the forthcoming workload requirement exceeds a utilization threshold and in turn, directs one or more cooling systems towards the corresponding subsystem according.Type: ApplicationFiled: July 17, 2012Publication date: January 23, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diyanesh Babu Vidyapoornachary Chinnakkonda, Edgar Rolando Cordero, Timothy J. Dell, Joab D. Henderson, Anil B. Lingambudi, Girisankar Paulraj