Patents by Inventor Timothy J. Fisher

Timothy J. Fisher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11036427
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a data access command which corresponds to data stored on NVRAM at a logical block address, and using content-addressable memory (CAM) to determine whether the logical block address corresponds to an active read modify write operation. In response to determining that the logical block address corresponds to an active read modify write operation, the data access command is satisfied using a first procedure. However, in response to determining that the logical block address does not correspond to an active read modify write operation, the data access command is satisfied using a second procedure. Moreover, using the CAM to determine whether the logical block address corresponds to an active read modify write operation is completed in a single clock cycle of the CAM.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kevin E. Sallese, Timothy J. Fisher
  • Patent number: 10963327
    Abstract: Non-volatile memory block management. A method according to one embodiment includes calculating an error count margin threshold for each of the at least some non-volatile memory blocks of a plurality of non-volatile memory blocks. A determination is made as to whether the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded. A memory block management function is triggered upon determining that the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: March 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Roman Pletka, Sasa Tomic
  • Patent number: 10942662
    Abstract: A computer-implemented method, according to one embodiment, includes: calibrating a first block of storage space in memory, identifying a page in the calibrated first block having a highest RBER, and determining whether the RBER of the identified page is greater than an error correction code limit. In response to determining that the RBER of the identified page is not greater than the error correction code limit, a determination is made as to whether the RBER of the identified page is greater than a relocation limit. In response to determining that the RBER of the identified page is not greater than a relocation limit, another determination is made as to whether the first block has been excessively calibrated. Furthermore, in response to determining that the first block has been excessively calibrated, data in the first block relocated to a second block of storage space in the memory.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sasa Tomic, Nikolaos Papandreou, Roman A. Pletka, Nikolas Ioannou, Aaron D. Fry, Timothy J. Fisher
  • Patent number: 10884914
    Abstract: A technique for garbage collection in a storage system includes generating regrouping metadata for one or more pages of at least two logical erase blocks (LEB). The regrouping metadata indicates an associated stream for each of the pages. Multiple of the LEBs that include valid pages associated with a first stream are selected, based on the regrouping metadata, for regrouping. The valid pages associated with the first stream from the selected LEBs are regrouped into a new LEB.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Razik S. Ahmed, Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Jason Ma, Matthew R. Orr, Roman A. Pletka, Lincoln T. Simmons, Sasa Tomic
  • Patent number: 10831651
    Abstract: A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. Moreover, the program instructions are readable and/or executable by a controller to cause the controller to perform a method which includes: assigning data having a first heat to a first data stream, assigning data having a second heat to a second data stream, and writing the data streams simultaneously, in parallel, to page-stripes having a same index across a series of planes of memory. The writing of the first data stream begins at an opposite end of the series of planes as the writing of the second data stream, the writing of the streams being toward one another. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Roman A. Pletka, Sasa Tomic
  • Publication number: 20200319821
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a data access command which corresponds to data stored on NVRAM at a logical block address, and using content-addressable memory (CAM) to determine whether the logical block address corresponds to an active read modify write operation. In response to determining that the logical block address corresponds to an active read modify write operation, the data access command is satisfied using a first procedure. However, in response to determining that the logical block address does not correspond to an active read modify write operation, the data access command is satisfied using a second procedure. Moreover, using the CAM to determine whether the logical block address corresponds to an active read modify write operation is completed in a single clock cycle of the CAM.
    Type: Application
    Filed: April 4, 2019
    Publication date: October 8, 2020
    Inventors: Kevin E. Sallese, Timothy J. Fisher
  • Publication number: 20200301768
    Abstract: A computer-implemented method, according to one embodiment, includes: performing a first read of one or more pages in a first page region of a first block. In response to determining that the highest RBER experienced during the first read is not in a first predetermined range, a first calibration procedure is performed on the one or more pages. A second read of the one or more pages is performed. In response to determining that the highest RBER experienced during the second read is not in a second predetermined range, a second calibration procedure on the one or more pages is performed, and a third read of the one or more pages is performed. In response to determining that the highest RBER experienced during the third read is not in the second predetermined range, a reliability counter which corresponds to the first page region of the first block is incremented.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 24, 2020
    Inventors: Nikolaos Papandreou, Roman A. Pletka, Sasa Tomic, Nikolas Ioannou, Charalampos Pozidis, Timothy J. Fisher, Aaron D. Fry
  • Patent number: 10783024
    Abstract: A computer-implemented method, according to one embodiment, includes: detecting that an error count resulting from reading a first page in a block of storage space in memory is above a first threshold, and reading a second page in the block of storage space. The second page is one which had a highest error count of the pages in the block of storage space following a last calibration of the block of storage space. Moreover, a determination is made as to whether an error count resulting from reading the second page is above the first threshold. In response to determining that the error count resulting from reading the second page is above the first threshold, the block of storage space is calibrated. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sasa Tomic, Timothy J. Fisher, Nikolaos Papandreou, Roman A. Pletka, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry
  • Patent number: 10732846
    Abstract: A computer-implemented method according to one embodiment includes determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values for the data written to the non-volatile memory block are calculated, the values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The overall threshold voltage shift values are stored. A base threshold voltage shift (TVSBASE) value, the one or more TVS? values, or both the TVSBASE value and the one or more TVS? values are re-calibrated during a background health check after a predetermined number of background health checks without calibration are performed.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Roman A. Pletka, Charalampos Pozidis, Sasa Tomic
  • Publication number: 20200192735
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a multi-page read request and predicting whether using a multi-plane read operation to read pages of storage space in memory which correspond to the multi-page read request will result in a bit error rate that is in a predetermined range. In response to predicting that using the multi-plane read operation to read the pages will not result in a bit error rate that is in the predetermined range, a threshold voltage shift (TVS) value is computed for the multi-plane read operation. Furthermore, the pages are read using the multi-plane read operation with the computed TVS. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Inventors: Nikolas Ioannou, Nikolaos Papandreou, Roman A. Pletka, Sasa Tomic, Charalampos Pozidis, Aaron D. Fry, Timothy J. Fisher, Kevin E. Sallese
  • Publication number: 20200174664
    Abstract: A computer-implemented method, according to one embodiment, includes: calibrating a first block of storage space in memory, identifying a page in the calibrated first block having a highest RBER, and determining whether the RBER of the identified page is greater than an error correction code limit. In response to determining that the RBER of the identified page is not greater than the error correction code limit, a determination is made as to whether the RBER of the identified page is greater than a relocation limit. In response to determining that the RBER of the identified page is not greater than a relocation limit, another determination is made as to whether the first block has been excessively calibrated. Furthermore, in response to determining that the first block has been excessively calibrated, data in the first block relocated to a second block of storage space in the memory.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 4, 2020
    Inventors: Sasa Tomic, Nikolaos Papandreou, Roman A. Pletka, Nikolas Ioannou, Aaron D. Fry, Timothy J. Fisher
  • Publication number: 20200117527
    Abstract: A computer-implemented method, according to one embodiment, includes: detecting that an error count resulting from reading a first page in a block of storage space in memory is above a first threshold, and reading a second page in the block of storage space. The second page is one which had a highest error count of the pages in the block of storage space following a last calibration of the block of storage space. Moreover, a determination is made as to whether an error count resulting from reading the second page is above the first threshold. In response to determining that the error count resulting from reading the second page is above the first threshold, the block of storage space is calibrated. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Application
    Filed: October 12, 2018
    Publication date: April 16, 2020
    Applicant: International Business Machines Corporation
    Inventors: Sasa Tomic, Timothy J. Fisher, Nikolaos Papandreou, Roman A. Pletka, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry
  • Patent number: 10621051
    Abstract: A controller-implemented method, according to one embodiment, includes: examining, by the controller, each of a plurality of journal entries from at least one journal beginning with a most recent one of the journal entries in a most recent one of the at least one journal and working towards an oldest one of the journal entries in an oldest one of the at least one journal, the journal entries corresponding to one or more updates made to one or more logical to physical table (LPT) entries of a LPT; determining, by the controller, whether a current LPT entry, which corresponds to a currently examined journal entry, has already been updated; and discarding, by the controller, the currently examined journal entry in response to determining that the current LPT entry has already been updated.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Roman A. Pletka, Lincoln T. Simmons, Sasa Tomic
  • Publication number: 20200104071
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a stream of data, and selecting more than one block of memory to write the stream of data to. The selected blocks of memory are in a memory that includes a plurality of blocks. Moreover, the data is written across the selected blocks of memory in parallel. The blocks of memory are also selected such that no two or more of the selected blocks of memory have an effect on a read apparent voltage of a same one of the plurality of blocks in the memory. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 2, 2020
    Inventors: Kevin E. Sallese, Timothy J. Fisher, Adalberto G. Yanes, Jason Szecheong Ma, Charles A. Keller, Aaron D. Fry, Van Huynh, Nikolaos Papandreou
  • Patent number: 10592110
    Abstract: A technique for adapting over-provisioning space in a storage system includes determining one or more workload characteristics in the storage system. Over-provisioning space in the storage system is then adjusted to achieve a target write amplification for the storage system, based on the workload characteristics.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Thomas Parnell, Roman A. Pletka, Sasa Tomic
  • Patent number: 10579270
    Abstract: A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. Moreover, the program instructions are readable and/or executable by a processor to cause the processor to perform a method which includes: maintaining a first open logical erase block for user writes, and a second open logical erase block for relocate writes. A first data stream having the user writes is received, and transferred to the first open logical erase block. A second data stream having the relocate writes is also received, and transferred to the second open logical erase block. Furthermore, a third data stream is received, and is mixed with the first, second, and/or another data stream in response to determining that an open logical erase block is not available for assignment to the third data stream.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Roman A. Pletka, Sasa Tomic
  • Publication number: 20200066355
    Abstract: A computer-implemented method, according to one embodiment, includes: detecting that a calibration of a first page group has been triggered, and evaluating a hierarchical page mapping to determine whether the first page group correlates to one or more other page groups in non-volatile memory. In response to determining that the first page group does correlate to one or more other page groups in the non-volatile memory, a determination is made as to whether to promote at least one of the one or more other page groups for calibration. In response to determining to promote at least one of the one or more other page groups for calibration, the first page group and the at least one of the one or more other page groups are calibrated. Moreover, each of the page groups includes one or more pages in non-volatile memory.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Inventors: Nikolaos Papandreou, Sasa Tomic, Roman A. Pletka, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry, Timothy J. Fisher
  • Patent number: 10552243
    Abstract: Technology for handling page size mismatches when DPL-CLR is performed at multiple levels of a data storage system (for example, RAID level and flash card level). A “corrective DPL” corrects only a portion of the data that would make up a page at the level at which the data is stored (that is, the “initial DPL level”), and, after that, a partially corrected page of data is formed and stored in data storage, with the partially corrected page: (i) having a page size characteristic of the initial DPL; (ii) including the part of the data corrected by the corrective DPL; and (iii) further including other data. In some embodiments, the other data has a pattern that indicates that it is invalid, erroneous data, such that an error message will be returned if this portion of the data is attempted to be read.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Roman A. Pletka, Timothy J. Fisher, Robert E. Galbraith, Kevin E. Sallese, Christopher M. Dennett
  • Patent number: 10528424
    Abstract: A computer-implemented method, according to one embodiment, includes: detecting at least one read of a logical page straddled across codewords, storing an indication of a number of detected reads of the straddled logical page, and relocating the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page. When relocated, the logical page is written to the different physical location in a non-straddled manner. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Nikolas Ioannou, Thomas Parnell, Roman A. Pletka, Sasa Tomic
  • Patent number: 10417088
    Abstract: A data protection technique combines error correcting code and redundant array of independent disk functionality for a non-volatile memory (NVM) array of a data storage system. The technique includes receiving, by a controller, data for storage in the NVM. In response to receiving the data for storage in the NVM array, the controller forms first component codewords based on encodings with a first level code of respective first portions of the data. In response to receiving the data for storage in the NVM array, the controller forms a second component codeword based on an encoding with a second level code of a second portion of the data and the first component codes. The controller stores a respective portion of each of the first and second component codeswords on packages of the NVM array. The storing achieves maximum equal spreading of each of the component codewords across all of the packages.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: September 17, 2019
    Inventors: Timothy J. Fisher, Thomas Mittelholzer, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis, Andrew D. Walls