Abstract: In at least one embodiment, a data storage system includes a non-volatile memory array including a plurality of blocks of physical memory, each including multiple pages. The data storage system further includes a controller that maintains a data structure identifying blocks of physical memory in the memory array that currently do not store valid data. The controller, responsive to receipt of a write input/output operation (IOP) specifying an address and write data, selects a particular block from among the blocks identified in the data structure prior to a dwell time threshold for the particular block being satisfied, programs a page within the selected block with the write data, and associates the address with the selected block.

Abstract: In at least one embodiment, a data storage system includes a non-volatile memory array, such as a flash memory array, and a controller coupled to the memory array. The controller records, for each of a plurality of valid pages in the memory array, a respective indication of a dwell time of each valid page.

Abstract: In at least one embodiment, a non-volatile memory array including a plurality of blocks each including a plurality of physical pages is controlled by a controller. The controller implements a plurality of nested page retirement classes each defined by a respective one of a plurality of different nested subsets of page indices of physical pages within the plurality of blocks that are to be considered retired from use. For each block among the plurality of blocks, the controller updating an indication of a page retirement class to which the block belongs in response to detection of a retirement-causing error in a data page stored in a physical page of the block. The controller forms block stripes for storing data from the plurality of blocks based on the page retirement classes of the blocks.

Abstract: An apparatus, according to one embodiment, includes: one or more memory devices, each memory device comprising non-volatile memory configured to store data, and a memory controller connected to the one or more memory devices. The memory controller is configured to: detect at least one read of a logical page straddled across codewords, store an indication of a number of detected reads of the straddled logical page, and relocate the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page, wherein the logical page is written to the different physical location in a non-straddled manner. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A controller-implemented method, according to one embodiment, includes: restoring a valid snapshot of a LPT from the non-volatile random access memory, examining each journal entry from at least one journal beginning with a most recent one of the journal entries in a most recent one of the at least one journal and working towards an oldest one of the journal entries in an oldest one of the at least one journal, the journal entries corresponding to updates made to one or more entries of the LPT, determining whether a current LPT entry which corresponds to a currently examined journal entry has already been updated, using the currently examined journal entry to update the current LPT entry in response to determining that the current LPT entry has not already been updated, and discarding the currently examined journal entry in response to determining that the current LPT entry has already been updated.

Abstract: A method, according to one embodiment, includes: receiving a recirculation command, performing a coarse page lookup to determine valid ones of logical pages to be recirculated, issuing write commands for the valid logical pages, requesting performance of a fine page lookup on source physical addresses containing the valid logical pages to verify the valid logical pages, receiving verified valid logical pages resulting from the fine page lookup, and sending the write commands corresponding to the verified valid logical pages. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A computer processor determines an over-provisioning ratio and a host write pattern. The computer processor determines a write amplification target based on the host write pattern and the over-provisioning ratio. The computer processor determines a staleness threshold, wherein the staleness threshold corresponds to a ratio of valid pages of a block to total pages of the block. The computer processor erases a first block having a staleness which exceeds the staleness threshold.

Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.

Abstract: In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values configured to track temporary changes with respect to changes in the underlying threshold voltage distributions due to retention and/or read disturb errors. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block, the one or more overall threshold voltage shift values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The one or more overall threshold voltage shift values are stored.

Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.

Abstract: In at least one embodiment, a controller of a non-volatile memory array retires physical pages within the non-volatile memory array on a page-by-page basis. The physical pages retired by the controller include a first physical page sharing a common set of memory cells with a second physical page. While the first physical page is retired, the controller retains the second physical page as an active physical page, writes dummy data to the first physical page, and writes data received from a host to the second physical page.

Abstract: In one embodiment, a method includes maintaining a first open logical erase block for user writes, maintaining a second open logical erase block for relocate writes, wherein the first and second open logical erase blocks are different logical erase blocks, receiving a first data stream having the user writes, transferring the first data stream to the first open logical erase block, receiving a second data stream having the relocate writes, and transferring the second data stream to the second open logical erase block. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A mechanism is provided for performing de-duplication process on a set of non-volatile memories as part of another process routinely performed on the set of non-volatile memories. A hash value of data stored at a first physical location in a non-volatile memory in the set of non-volatile memories is received from a non-volatile memory controller associated with the non-volatile memory. Responsive to the hash value matching one or more existing hash values for data stored at one or more other physical locations in the set of non-volatile memories, an optimal physical location is identified from the first physical location and the one or more other physical locations. Responsive to identifying the optimal physical location, a set of logical addresses associated with the hash values is updated to point to the optimal physical location. The non-optimal physical locations are further invalidated in order that the non-optimal physical locations are erased.

Abstract: Non-volatile memory block management. A method according to one embodiment includes calculating an error count margin threshold for each of the at least some non-volatile memory blocks of a plurality of non-volatile memory blocks. A determination is made as to whether the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded. A memory block management function is triggered upon determining that the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded.

Abstract: A method, according to one embodiment, includes repeating the following sequence at least until a page stripe of a memory cache has at least a predetermined amount of data stored therein: receiving a compressed logical page of data, finding an open codeword having an amount of available space which is greater than or equal to a size of the compressed logical page, and storing the compressed logical page in the open codeword having the amount of available space which is greater than or equal to a size of the compressed logical page. The compressed logical page does not straddle out of the open codeword. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values configured to track temporary changes with respect to changes in the underlying threshold voltage distributions due to retention and/or read disturb errors. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block, the one or more overall threshold voltage shift values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The one or more overall threshold voltage shift values are stored.

Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.

Abstract: Techniques for data deduplication in a data storage system include comparing a first attribute of a received data page to first attributes of one or more stored data pages. In response to the first attribute matching one of the first attributes, a second attribute of the received data page is compared to second attributes of the one or more data pages. In response to the second attribute of the received data page matching one of the second attributes, a fingerprint of the received data page is compared to fingerprints of the one or more data pages. In response to the fingerprint of the received data page matching one of the fingerprints, the received data page is discarded and replaced with a reference to the corresponding data page already stored in the storage system. In response to first attribute, the second attribute, or the fingerprint of the received data page not matching, the received data page is stored.

Abstract: A data storage system includes a controller and a non-volatile memory array having a plurality of blocks each including a plurality of physical pages. The controller maintains a logical-to-physical translation (LPT) data structure that maps logical addresses to physical addresses and implements a first data protection scheme that stripes write data over the plurality of physical blocks. In response to a read request requesting data from a target page stripe, the controller detecting errors in multiple physical pages of the target page stripe. In responsive to detecting errors in multiple physical pages of the target page stripe, the controller scans the LPT data structure to identify a set of logical addresses mapped to the target page stripe and triggers recovery of the target page stripe by a higher level controller that implements a second data protection scheme, wherein triggering recovery includes transmitting the set of logical addresses to the higher level controller.

Abstract: Non-volatile memory block management. A method according to one embodiment includes determining a block health of at least some non-volatile memory blocks of a plurality of non-volatile memory blocks that are configured to store data. An error count margin threshold is calculated for each of the at least some non-volatile memory blocks. A determination is made as to whether the error count margin threshold of any of the at least some non-volatile memory blocks has been exceeded. A memory block management function is triggered upon determining that the error count margin threshold of any of the non-volatile memory blocks has been exceeded.