Abstract: LBIST resource parameters are used to control the data inputs for the signature generation process. These resource parameters include a LBIST pattern cycle counter, a channel input selected to input the MISR, and a channel load/unload shift counter. Properly setting one or more of these resource parameters to conditionally control those latch content values that get clocked into the MISR during the unload operation generates a three dimensional signature space.

Abstract: A BIST method that modifies the scan chain path and scan clocks to allow for distributed BIST test. In this distributed BIST concept, the Linear Feedback Shift Register (LFSR) and the Multiple Input Signature Register (MISR) are combined as an integral part of the scan chain, and each scan cycle is utilized as a test cycle.

Abstract: A method of LBIST testing of an entire chip (i.e. all logic and arrays are getting system clocks) enables finding intermittent fault in an area, such as the L1 cache. Latches such as GPTR latches can be set such that the L1 cache will no longer receive system clocks during LBIST testing. Logic causing an intermittent failure will no longer receive system clocks and hence will no longer cause intermittent LBIST signatures. LBIST testing can proceed on looking for the next failure, if one existed, or proving that the remaining logic contains no faults. Generally, a chip, has a basic clock distribution and control system that the chip is divided into a number (N) of functional units with each unit receiving system clocks from its own clock control macro. Each clock control macro receives an oscillator signal and a bit from the GPTR (General Purpose Test Register). All the functional units contain latches that are connected into one scan chain.

Abstract: Algorithmically generated test patterns are structured for efficient test of "scan path" logic devices. A look ahead pattern generation and simulation scheme achieves a pre-specified fault coverage. The fault simulation engine picks one of two paths at the end of each Tester Loop (TL) simulation: (1) restore to the state just prior to the current simulated Tester Loop and advance the pattern generators one state if an ineffective Tester Loop was found or (2) advance the pattern generators one state (from the end of the Tester Loop) if an effective Tester Loop was encountered. This basic technique can be modified to support parallel fault simulation by defining the pattern generator state at the start of the next tester loop (TL) state (TL.sub.n+1) to be one state advanced from the pattern generator state at the START of TL.sub.n. The pattern generator state for the start of all future TLs can be determined and parallel fault simulation is supported.