Abstract: An interposer is described to regulate the current in wafer test tooling. In one example, the interposer includes a first connection pad to couple to automated test equipment and a second connection pad to couple to a device under test. The interposer further includes an overcurrent limit circuit to connect the first and second connection pads and to disconnect the first and second connection pads when the current between the first and second connection pads is over a predetermined amount.

Abstract: Described herein is an apparatus and system of an electrostatic discharge circuit. The apparatus comprises: a clamp transistor with a terminal coupled to a node with a power supply; and a detector to determine when the power supply crosses a first threshold, the detector to generate a trigger signal to cause the clamp transistor to remain off when the power supply on the node is below the first threshold.

Abstract: An interposer is described to regulate the current in wafer test tooling. In one example, the interposer includes a first connection pad to couple to automated test equipment and a second connection pad to couple to a device under test. The interposer further includes an overcurrent limit circuit to connect the first and second connection pads and to disconnect the first and second connection pads when the current between the first and second connection pads is over a predetermined amount.

Abstract: Described herein is an apparatus and system of an electrostatic discharge circuit. The apparatus comprises: a clamp transistor with a terminal coupled to a node with a power supply; and a detector to determine when the power supply crosses a first threshold, the detector to generate a trigger signal to cause the clamp transistor to remain off when the power supply on the node is below the first threshold.

Abstract: In some embodiments, a power supply clamp may include a switchable discharge device configured to discharge an electrostatic discharge; and a control circuit configured to generate a control voltage to turn off the discharge device at a shutoff time, with the shutoff time being long enough to allow the electrostatic discharge though the discharge device but short enough to reduce a duration of a power-up current transient through the discharge device. Other embodiments may be described and claimed.

Abstract: A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width.

Abstract: A charged device model (CDM) electrostatic discharge (ESD) testing is carried out at wafer level. Wafer CDM pulses are repeatedly applied and monitored. The wafer CDM (WCDM) pulses are accomplished with a probe-mounted printed-circuit board and a high-frequency transformer that captures fast CDM pulses. Modeling of CDM and WCDM in the time and frequency domain illustrates the dominant effects, and shows that WCDM can reproduce all the major phenomena of package-level CDM testing.

Abstract: In some embodiments, a power supply clamp may include a switchable discharge device configured to discharge an electrostatic discharge; and a control circuit configured to generate a control voltage to turn off the discharge device at a shutoff time, with the shutoff time being long enough to allow the electrostatic discharge though the discharge device but short enough to reduce a duration of a power-up current transient through the discharge device. Other embodiments may be described and claimed.

Abstract: A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width.

Abstract: A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width.

Abstract: In some embodiments, an apparatus includes a power supply to generate a supply current; at least one optoisolator coupled to the power supply and responsive to the supply current to generate a charging current; a capacitor, coupled to the at least one optoisolator, to build up a charge in response to the charging current; and an actuating switch, coupled to the capacitor, to release the charge from the capacitor to generate a relay actuating current.

Abstract: A field detection device such as a micro-strip portion of a transmission line may detect an electric field and a magnetic field induced by current steps injected into the chassis coupled to a ground plane. The shield portions of the transmission line may be coupled to a first and a second port of an I/O connector. A measurement system coupled to the connector may determine the electric field and the magnetic field detected by the micro-strip. The measurement system may determine the electric field and magnetic field based on computing the sum and difference of the signals provided by the first port and the second port.

Abstract: A charged device model (CDM) electrostatic discharge (ESD) testing is carried out at wafer level. Wafer CDM pulses are repeatedly applied and monitored. The wafer CDM (WCDM) pulses are accomplished with a probe-mounted printed-circuit board and a high-frequency transformer that captures fast CDM pulses. Modeling of CDM and WCDM in the time and frequency domain illustrates the dominant effects, and shows that WCDM can reproduce all the major phenomena of package-level CDM testing.

Abstract: Apparatus and systems, as well as methods for using them, may include launching a pulse into an input port of a quarter-wave directional coupler having an thru port and an isolated port, and receiving a leading edge of the pulse as a voltage spike at an output port of the coupler. A switch may be activated to couple a pulse source to the input port. The impedance of the coupler may be selected to match the resistance of the switch added to the impedance of a charge line included in the pulse source.

Abstract: A field detection device such as a micro-strip portion of a transmission line may detect an electric field and a magnetic field induced by current steps injected into the chassis coupled to a ground plane. The shield portions of the transmission line may be coupled to a first and a second port of an I/O connector. A measurement system coupled to the connector may determine the electric field and the magnetic field detected by the micro-strip. The measurement system may determine the electric field and magnetic field based on computing the sum and difference of the signals provided by the first port and the second port.

Abstract: A multi-stack power supply clamp circuit for providing electrostatic discharge (ESD) protection to enhance performance of advanced submicron processes is provided. The clamp circuit includes a bias voltage generator with low leakage and high current drive capabilities, and means to lighten current load on the voltage generator through reduced gate leakage. The bias voltage generator includes a differential amplifier. The multi-stack clamp circuit provides voltage-tolerant ESD protection with optimized leakage, reduced sensitivity to operating conditions, and tolerance of increased gate current in new process technologies.

Abstract: An electrostatic discharge protection circuit is provided having a first electrically conductive element (such as a current sinking transistor) to couple between a power source and a first node. The first electrically conductive element has a control input terminal. A discharge path control circuit having an output terminal couples to the control input terminal of the first electrically conductive element. A timer circuit having an output terminal couples to the input terminal of the discharge path control circuit. A ring oscillator timer circuit having an output terminal couples to an input terminal of the timer circuit. The ring oscillator timer circuit may include a series of inverter circuits and/or counter circuits (such as flip-flop circuits).

Abstract: Apparatus and systems, as well as methods and articles, may operate to transmit an initial pulse to a directional coupler, where the initial pulse has an initial amplitude and a timed overshoot of a selected duration. Further activities may include stepping down the initial amplitude to an amplitude approximately equal to the initial amplitude times a mode reflection coefficient squared. A tuning stub may be coupled to a charge line to transmit the initial pulse, and decoupled from the charge line to refrain from receiving an echo pulse associated with the initial pulse.

Abstract: A multi-stack power supply clamp circuit for providing electrostatic discharge (ESD) protection to enhance performance of advanced submicron processes is provided. The clamp circuit includes a bias voltage generator with low leakage and high current drive capabilities, and means to lighten current load on the voltage generator through reduced gate leakage. The bias voltage generator has includes a differential amplifier. The multi-stack clamp circuit provides voltage-tolerant ESD protection with optimized leakage, reduced sensitivity to operating conditions, and tolerance of increased gate current in new process technologies.

Abstract: In some embodiments, an apparatus includes an electronic device that has a ground to receive an electrostatic discharge. A radiation detector, mounted on the electronic device, generates a differential signal in response to the electrostatic discharge.