Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit comprises a charge protection device that is reverse body biased when the integrated circuit is in normal operation.

Abstract: A circuit is provided that has an output buffer connected to one of a plurality of output pads. A power source is connected to one of the plutrality of output pads. A first pair of capacitors is connected to the power source. A second pair of capacitors is connected to the first pair of capacitors and the power source. A first pair of signal sources are connected to the first pair of capacitors. A second pair of signal sources connected to the second pair of capacitors. The first pair of signal sources and the second pair of signal sources control discharge to the power source and recharge to the power source of the first pair of capacitors and the second pair of capacitors to cancel out noise caused by either a voltage or current switching transient. Also, a method is provided for sending data to an output buffer, determining data to be clocked the next cycle, and controlling a charge-pump circuit to compensate for a voltage transition from one of high-to-low and low-to-high.

Abstract: Through silicon optical modulators (TSOM) formed in a silicon integrated circuit comprise a grating array of MOSFET elements. The TSOM's provide optical phase shifts from different areas which contrast with one another coherently. Phase modulated optical beams reflected from the grating interfere with one another and allow the modulation to be easily detected off-chip. In one embodiment, a two dimensional array has a gate structure which is used to modulate a light beam by forming accumulation layers. In another embodiment, a one dimensional array is formed using parallel gate strips, where alternate gates are used as reference reflectors.

Abstract: Through silicon optical modulators (TSOM) formed in a silicon integrated circuit comprise an array of MOSFET elements which cause optical phase shifts of reflected light to identify a state of a signal. A polarization of the reflected light is modified by the phase shift and transmits the signal. The polarization of reflected light can be controlled by the angle of the incident light, by polarizing optical slits fabricated in the modulator, or by using a polarized mirror. Either embodiment allows the polarized reflected light to be nulled out. As such, a polarization of the reflected light is altered when the signal is applied to the modulator. The altered polarization can then be detected.

Abstract: An optical modulator that modulates light through the semiconductor substrate through the back side of an integrated circuit die. In one embodiment, the optical beam enters through the back side of the semiconductor substrate at a first location. The path of the optical beam is altered such that the optical beam passes through and along and through a path parallel or nearly parallel to the front side of the semiconductor substrate. In one embodiment, the optical modulator includes a charged layer through which the optical beam is directed along the path parallel or nearly parallel to the front side. In one embodiment, the charge concentration of free charge carriers is modulated in response to a signal of the integrated circuit die, resulting in modulation of the optical beam.

Abstract: A through silicon optical modulator alters a phase of a light beam which enters the back of a silicon die. The modulator can be formed as a PMOS transistor fabricated in an n-well, or can be an NMOS transistor having a negative gate to substrate voltage. By modulating the well voltage (or gate potential) the phase of a portion of the reflected light is altered. Two accumulation layers are selectively formed in the light path which is reflected from the transistor gate electrode. The phase change is detected to provide a signal from the integrated circuit having the through silicon optical modulator structure.

Abstract: Circuitry is provided which increases the efficiency of electrostatic discharge (ESD) power supply clamping circuitry to sink larger currents during an ESD event on a power supply node. Voltage clamp circuits capable of providing ESD protection to a supply node are described. The voltage clamp circuits include a discharge transistor which is controlled by a control circuit during an ESD event. The control circuit operates in response to a voltage provided on the protected supply node. One embodiment provides a P-channel MOS transistor and a control circuit which drives the gate of the transistor. Another embodiment provides an N-channel MOS transistor and a control circuit which drives the gate of the transistor.

Abstract: Clamp circuitry capable of providing ESD protection to a high voltage supply connection is provided. The clamp circuitry increases the area efficiency of ESD power supply clamping circuitry to sink larger currents during an ESD event, while maintaining backward compatibility with the higher voltage requirements of older ICs. The voltage clamp circuits include two discharge transistors which are controlled by a control circuit. The control circuit couples the gates of the discharge transistors to ground during an ESD event.

Abstract: Electrostatic discharge protection circuits adapted for use in low voltage CMOS processes have at least one PFET in the primary charge conduction path, and timer circuits configured to enable the primary conduction path during ESD events and to disable the primary conduction path during steady state conditions.In a further aspect of the present invention, bias circuits for maintaining steady state gate voltages below the dielectric breakdown level are included.In a still further aspect of the present invention a bridge circuit couples a first power supply node to a second power supply node, where the second power supply node is coupled to an ESD protection circuit.

Abstract: An arrangement for preventing damage to a circuit of an integrated circuit chip due to the occurrence of voltage introduced externally to the integrated circuit is disclosed. The arrangement generally has a timer circuit, a clamping circuit, and an override circuit. The clamping circuit is coupled between an input and ground such that voltages and currents applied to the input are shunted to ground for a first length of time. The timer circuit is coupled to the input and passes a voltage applied to the input for the first length of time. The output of the timer circuit is disabled at the expiration of the first length of time. The override circuit disables the clamping circuit a second length of time after a power supply voltage exceeds a predetermined level.

Abstract: An arrangement for preventing damage to a circuit of an integrated circuit due to the occurrence of voltage transients introduced externally to the integrated circuit. Generally, the arrangement provides protection against voltage transients for certain circumstances and disables such protection for other circumstances. Transient protection is enabled when the power of the transient would cause breakdown of the transistors of the integrated circuit. Otherwise, transient protection is disabled.

Abstract: An arrangement for preventing damage to a circuit of an integrated circuit due to the occurrence of voltage transients introduced externally to the integrated circuit. According to one embodiment, the voltage transients are due to electrostatic discharge (ESD). The arrangement comprises a latch for coupling to an input pad of the integrated circuit. The latch asserts a first signal in response to sensing the occurrence of the voltage transient at the input pad. A transient protection circuit is coupled to the input pad for coupling the input pad to ground in response to the latch asserting the first signal such that current associated with the voltage transient is shunted to ground. A circuit is coupled to the latch for preventing the latch from asserting the first signal in response to the occurrence of the voltage transient if a predetermined condition exists.

Abstract: A method and an apparatus for protecting an integrated circuit from electrostatic discharge. In one embodiment, a voltage reduction circuit coupled to a termination circuit are coupled between a power supply and ground. The disclosed voltage reduction circuit utilizes a cantilevered diode string coupled to a clad network. Coupled to the voltage reduction circuit and the termination circuit is a voltage divider circuit which is coupled between the power supply and ground. The voltage supplied to the voltage reduction circuit and the termination circuit is a lower voltage than the steady state power supply voltage and is a tolerable voltage for gate oxides of a low voltage process. In another embodiment of the present invention, a voltage reduction circuit utilizing a stacked gate scheme is coupled between the power supply and ground. A voltage divider circuit is used in this embodiment to provide a bias voltage. The bias voltage is supplied to the voltage reduction circuit and a control circuit.

Abstract: A method and an apparatus protecting an integrated circuit from electrostatic discharge. In one embodiment, a method of coupling the gate of an ESD protection transistor high during an ESD event to ensure a more efficient protection device is described. The method uses static fixed parallel plate capacitances coupled to the gate of an ESD protection device to place the ESD protection device above threshold during an ESD event. The fixed parallel plate capacitances form capacitors between the gate-and-drain and gate-and-source of the ESD protection device resulting in static capacitive gate coupling which is more calculable and controllable. The ratios of the capacitances are set so as to bias the gate of the ESD protection device above threshold during an ESD event, thus allowing the ESD protection device to sink current during the ESD event.

Abstract: In device requiring ESD protection, a bias network is used to augment the diode string to distribute small but significant forward current to the diodes. Also employed is the use of cantilever diodes which provide PNP Darlington gain block for ESD protection rather than for amplifying signals in bipolar ICs. In one embodiment, the termination is the principal element of device novelty and that which makes the protection device "stand-alone". The termination supplies final base current to the gain block for a limited amount of time, so that ESD charge can be shunted harmlessly through the PNP chain, but assures that the structure draws no current from a stable power supply long term. The entire structure is able to absorb noise spikes as well as ESD pulses. The termination also makes provisions for discharging its capacitor between ESD pulses, as is necessary for standardized testing.

Abstract: A furniture structure for chairs, benches and the like consisting of substantially planar members which interlock and reversibly unlock without the use of tools or separate fasteners, comprises two sides, a seat member, a back and a front, the sides each having an upper edge, and the seat member including a forward edge and a rear edge. An interlocking sector on each of the sides interlocks with the seat member, the back and the front without the need for tools or separate fasteners. The interlocking sector includes first and second members on each of the sides for frictionally engaging the forward and rear edges of the seat member, respectively, in opposite directions. A third member on each of the sides frictionally engages the seat member in a direction substantially perpendicular to the opposite directions.

Abstract: A staircase cabinet comprises a plurality of treads each having an outer edge, an inner edge and a back surface; a pair of outer stringers both for defining opposed walls of the cabinet and supporting the outer edges of each tread; an inner stringer for supporting the inner edges of each tread; and fasteners for attaching the treads to the inner stringer and the outer stringers in alternating arrangement on respective opposite sides of the inner stringer to define an alternating staircase for use between a lower level and an upper level, the back surface of the treads and the outer stringers defining a cabinet space. The outer stringers comprise planar wooden sheets having an outer surface, and the fasteners pass only partially through the planar members to maintain the outer surface unbroken by the fasteners.

Abstract: A device for protecting semiconductor devices during excess energy events. The device uses p-MOS field effect transistors in a common n-well with a common gate configuration. An input is coupled to the source of a first p-type transistor and to the n-well. The first transistor is coupled through a series resistor to a second p-MOS transistor. The drains of each transistor are coupled to ground and gate aided breakdown reduces the voltage at which breakdown occurs.

Abstract: A high efficiency solar heating system comprising a plurality of hollow modular units each for receiving a thermal storage mass, the units being arranged in stacked relation in the exterior frame of a building, each of the units including a port for filling the unit with the mass, a collector region and a storage region, each region having inner and outer walls, the outer wall of the collector region being oriented for exposure to sunlight for heating the thermal storage mass; the storage region having an opening therein and the collector region having a corresponding opening, the openings being joined for communicating the thermal storage mass between the storage and collector regions by thermosiphoning; the collector region being disposed substantially below and in parallel relation to the storage region in the modular unit; and the inner wall of the collector region of each successive modular unit in the stacked relation extending over the outer wall of the storage region of the next lower modular unit in

Abstract: A combination solar collector, thermal storage and heating module for mounting in a building framework comprising a hollow panel member for receiving a thermal storage mass, including an outer wall and an inner wall; opposed pairs of sidewalls and end walls sealed to the inner and outer walls for connecting the corresponding perimeters of the inner and outer walls, thereby defining an enclosed chamber; a plurality of individual connections each of the connections forming a joint between the inner wall and the outer wall for maintaining the rigidity of the walls when the chamber is filled with the mass; and a port in the panel member for filling the panel member with the mass. Various modifications and alternatives are disclosed including several structures for attaching the module to the building framework, and additional modifications for increasing solar absorption and decreasing heat loss from the building.