Abstract: A computer-implemented method includes, in a transactional memory environment comprising a plurality of processors, identifying one or more selected processors and identifying one or more coherence privilege state indicators. The one or more coherence privilege state indicators are associated with the one or more selected processors. A coherence privilege behavioral pattern is determined based on the one or more coherence privilege state indicators. A corresponding computer program product and computer system are also disclosed.

Abstract: A computer-implemented method includes, in a transactional memory environment comprising a plurality of processors, identifying one or more selected processors and identifying one or more coherence privilege state indicators. The one or more coherence privilege state indicators are associated with the one or more selected processors. A coherence privilege behavioral pattern is determined based on the one or more coherence privilege state indicators. A corresponding computer program product and computer system are also disclosed.

Abstract: A delay facility is provided in which program execution may be delayed until a predefined event occurs, such as a comparison of memory locations results in a true condition, a timeout is reached, an interruption is made pending or another condition exists. The delay facility includes one or more compare and delay machine instructions used to delay execution. The one or more compare and delay instructions may include a 32-bit compare and delay (CAD) instruction and a 64-bit compare and delay (CADG) instruction.

Abstract: A processor in a multi-processor configuration is configured perform dynamic address translation from logical addresses to real address and to detect memory conflicts for shared logical memory in transactional memory based on logical (virtual) addresses comparisons.

Abstract: Sharing snapshots between restoration and recovery. A snapshot to be used for recovery and restoration is obtained. The snapshot includes restoration state for a plurality of architected registers. The plurality of architected registers includes one or more architected registers associated with an instruction to alter an execution path and one or more architected registers associated with a save request. At least one architected register of the plurality of architected registers is restored, based on a request. The request is a recovery request to recover at least one architected register associated with the instruction to alter the execution path or a restoration request to restore at least one architected register associated with the save request.

Abstract: Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. Prior to execution of the prefetch request, a processor determines whether the prefetch request conflicts with a transaction of the local processor. A processor responds to a determination that the priority of the remote processor is greater than priority of the local processor by (i) aborting the transaction (ii) executing the prefetch request, and (iii) providing requested prefetch data to the remote processor.

Abstract: A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by either another central processing unit or the Input/Output subsystem. Based on the inspected data, transactional execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs. For instance, when the instruction executes, the processor is in a nonconstrained transaction execution mode, and the transaction nesting depth is one at the beginning of the instruction, a second operand of the instruction is inspected, and based on the inspected data, transaction execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs, such as the value of the second operand becomes a prespecified value or a time interval is exceeded.

Abstract: A load request to restore a plurality of architected registers is obtained. Based on obtaining the load request, one or more architected registers of the plurality of architected registers are restored. The restoring uses a snapshot that maps architected registers to physical registers to replace one or more physical registers currently assigned to the one or more architected registers with one or more physical registers of the snapshot corresponding to the one or more architected registers.

Abstract: One or more architected registers are restored from a snapshot previously taken of the one or more architected registers. The snapshot indicates one or more physical registers previously assigned to the one or more architected registers. The restoring replaces the one or more physical registers currently assigned to the one or more architected registers with the one or more physical registers previously assigned to the one or more architected registers as indicated by the snapshot. A determination is made as to the validity of the one or more architected registers restored using the snapshot. The determining validity includes checking memory locations associated with the one or more architected registers to determine whether contents of the one or more architected registers have changed since the snapshot was taken. If the contents of the one or more architected registers have not changed, the one or more architected registers are valid.

Abstract: Register restoration invalidation based on a context switch. A context switch from one executing entity to another executing entity is detected. Based on detecting the context switch, an entry of a snapshot stack to be invalidated is selected. The entry of the snapshot stack provides an indication of a snapshot. The snapshot includes an assignment of one or more physical registers to one or more architected registers. The entry of the snapshot stack selected for invalidation is invalidated.

Abstract: A reload multiple instruction is used to restore a set of architected registers saved by a spill multiple instruction. The reload multiple instruction is executed, and the executing includes determining the set of architected registers to be restored, which is specified by the reload multiple instruction. The set of architected registers is restored from a selected snapshot that maps architected registers to physical registers. The restoring replaces one or more physical registers currently assigned to one or more architected registers of the set of architected registers with one or more physical registers of the selected snapshot corresponding to the set of architected registers.

Abstract: Register restoration or register reloading is selected. A restoration request to restore a plurality of architected registers is obtained. A determination is made as to whether a snapshot associated with the plurality of architected registers is valid. The snapshot provides in-core values for the plurality of architected registers. Based on the snapshot being valid, a determination is made as to whether the snapshot is to be used to recover an individual architected register of the plurality of architected registers. Based on determining the snapshot is to be used, the snapshot is used to recover the individual architected register. Based on determining the snapshot is not to be used, memory is used to recover the individual architected register.

Abstract: Register restoration using recovery buffers. A restore request initiated by an application to restore one or more registers indicated by the restore request is obtained. The one or more registers are restored using a recovery buffer. The restoring scans the recovery buffer for the one or more registers indicated by the restore request, and restores the one or more registers using one or more values obtained from the recovery buffer.

Abstract: Selective register allocation. Based on determining that an unused physical register is unavailable for allocation, a physical register to be used for allocation is chosen from a selective group of physical registers. The selective group of physical registers is associated with a snapshot of one type of snapshot selected from a plurality of types of snapshots. The snapshot maps physical registers to architected registers. The physical register chosen for allocation is allocated.

Abstract: Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. Prior to execution of the prefetch request, a processor determines whether the prefetch request conflicts with a transaction of the local processor. A processor responds to a determination that the priority of the prefetch request is greater than priority of the transaction, by (i) aborting the transaction (ii) executing the prefetch request, and (iii) providing requested prefetch data to the remote processor.

Abstract: An aspect includes performing, for each of a plurality of hardware threads executing on a plurality of cores in a (SMP) computer system, receiving a value of a timer corresponding to the hardware thread, the timer counting a number of clock cycles since a last reset of the timer. The value of the timer is compared to a threshold value for the hardware thread, where the threshold value specifies a number of clock cycles. Based on the value of the timer meeting the threshold value, a control signal is sent to cause all hardware threads currently executing on the core to halt execution and data describing a state of the core is logged. Each of the timers corresponding to each of the plurality of hardware threads are configured to be reset, paused, and restarted independently of each of the other timers.

Abstract: A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.

Abstract: A Spin Loop Delay instruction. The instruction has a field associated therewith that indicates one or more conditions to be checked. Dispatching of the instruction is initially delayed. The instruction is subsequently dispatched based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.

Abstract: One aspect is an analysis system that includes a processor operably coupled to a memory and configured to perform a method. The method includes defining a set of workloads for a targeted multi-core computer system based on a plurality of metrics of interest to profile. A plurality of workload-to-core mappings is generated for the workloads on the targeted multi-core computer system. The workloads run on the targeted multi-core computer system based on the workload-to-core mappings to produce a mapping of the workloads to the metrics of interest as experimental data. A statistical analysis is applied on the experimental data to define a plurality of metric profiles for the targeted multi-core computer system.

Abstract: Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.