Patents by Inventor Timothy J. Slegel

Timothy J. Slegel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selectively blocking branch prediction for a predetermined number of instructions
    Patent number: 10019265
    Abstract: Embodiments relate to selectively blocking branch instruction predictions. An aspect includes computer implemented method for performing selective branch prediction. The method includes detecting, by a processor, a branch-prediction blocking instruction in a stream of instructions and blocking, by the processor, branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Ulrich Mayer, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel
  • PREFETCHING OF DISCONTIGUOUS STORAGE LOCATIONS IN ANTICIPATION OF TRANSACTIONAL EXECUTION
    Publication number: 20180189067
    Abstract: Discontiguous storage locations are prefetched by a prefetch instruction. Addresses of the discontiguous storage locations are provided by a list directly or indirectly specified by a parameter of the prefetch instruction, along with metadata and information about the list entries. Fetching of corresponding data blocks to cache lines is initiated. A processor may enter transactional execution mode and memory instructions of a program may be executed using the prefetched data blocks.
    Type: Application
    Filed: February 26, 2018
    Publication date: July 5, 2018
    Inventors: Fadi Y. Busaba, Dan F. Greiner, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel
  • Transaction abort instruction specifying a reason for abort
    Patent number: 9996360
    Abstract: A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Marcel Mitran, Timothy J. Slegel
  • Selectively controlling instruction execution in transactional processing
    Patent number: 9983882
    Abstract: Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Robert R. Rogers, Timothy J. Slegel
  • Selectively controlling instruction execution in transactional processing
    Patent number: 9983881
    Abstract: Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Robert R. Rogers, Timothy J. Slegel
  • Facilitating transaction completion subsequent to repeated aborts of the transaction
    Patent number: 9983915
    Abstract: Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brenton F. Belmar, Christian Jacobi, Randall W. Philley, Timothy J. Slegel
  • Transaction abort instruction specifying a reason for abort
    Patent number: 9983883
    Abstract: A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Marcel Mitran, Timothy J. Slegel
  • DYNAMIC RELEASING OF CACHE LINES
    Publication number: 20180136966
    Abstract: A computer-implemented method includes, in a transactional memory environment, identifying a transaction and identifying one or more cache lines. The cache lines are allocated to the transaction. A cache line record is stored. The cache line record includes a reference to the one or more cache lines. An indication is received. The indication denotes a request to demote the one or more cache lines. The cache line record is retrieved, and the one or more cache lines are released. A corresponding computer program product and computer system are also disclosed.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 17, 2018
    Inventors: Jonathan D. Bradbury, Michael Karl Gschwind, Chung-Lung K. Shum, Timothy J. Slegel
  • Transactional memory operations with write-only atomicity
    Patent number: 9971690
    Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic write-only mode ignoring conflicts to certain read-sets of a transaction during transactional execution. Write-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Chung-Lung K. Shum, Timothy J. Slegel
  • Dynamic releasing of cache lines
    Patent number: 9971629
    Abstract: A computer-implemented method includes, in a transactional memory environment, identifying a transaction and identifying one or more cache lines. The cache lines are allocated to the transaction. A cache line record is stored. The cache line record includes a reference to the one or more cache lines. An indication is received. The indication denotes a request to demote the one or more cache lines. The cache line record is retrieved, and the one or more cache lines are released. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Michael Karl Gschwind, Chung-Lung K. Shum, Timothy J. Slegel
  • Coherence protocol augmentation to indicate transaction status
    Patent number: 9971626
    Abstract: Embodiments relate to implementing a coherence protocol. An aspect includes sending a request for data to a remote processor and receiving by a processor a response from the remote processor. The response has a transaction status of a remote transaction on the remote processor. The processor adds the transaction status of the remote transaction on the remote processor in a local transaction interference tracking table.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: May 15, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Christian Jacobi, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel
  • Instruction to load data up to a specified memory boundary indicated by the instruction
    Patent number: 9959117
    Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: May 1, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel
  • Instruction to load data up to a dynamically determined memory boundary
    Patent number: 9959118
    Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 1, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel
  • Hardware transaction transient conflict resolution
    Patent number: 9952804
    Abstract: In an approach for resolving terminated transactions in a transactional memory environment, a processor initiates a hardware transaction in a computing environment, wherein the hardware transaction accesses a memory location, and wherein the hardware transaction includes a transaction begin indicator and a transaction end indicator. A processor detects a conflicting access of the memory location while executing the hardware transaction. A processor aborts the hardware transaction based on the conflicting access of the memory location. Hardware determines that the conflicting access of the memory location is a transient condition. A processor reinitiates the hardware transaction.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Instruction to load data up to a dynamically determined memory boundary
    Patent number: 9952862
    Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwartz, Timothy J. Slegel
  • FUNCTION VIRTUALIZATION FACILITY FOR FUNCTION QUERY OF A PROCESSOR
    Publication number: 20180107480
    Abstract: Selected installed function of a multi-function instruction is hidden such that even though a processor is capable of performing the hidden installed function, the availability of the hidden function is hidden such that responsive to the multi-function instruction querying the availability of functions, only functions not hidden are reported as installed.
    Type: Application
    Filed: December 8, 2017
    Publication date: April 19, 2018
    Inventors: Dan F. Greiner, Damian L. Osisek, Timothy J. Slegel
  • RESTRICTED INSTRUCTIONS IN TRANSACTIONAL EXECUTION
    Publication number: 20180107488
    Abstract: Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions.
    Type: Application
    Filed: December 8, 2017
    Publication date: April 19, 2018
    Inventors: Dan F. Greiner, Christian Jacobi, Timothy J. Slegel
  • Hardware transaction transient conflict resolution
    Patent number: 9946494
    Abstract: In an approach for resolving terminated transactions in a transactional memory environment, a processor initiates a hardware transaction in a computing environment, wherein the hardware transaction accesses a memory location, and wherein the hardware transaction includes a transaction begin indicator and a transaction end indicator. A processor detects a conflicting access of the memory location while executing the hardware transaction. A processor aborts the hardware transaction based on the conflicting access of the memory location. Hardware determines that the conflicting access of the memory location is a transient condition. A processor reinitiates the hardware transaction.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Instruction to load data up to a specified memory boundary indicated by the instruction
    Patent number: 9946542
    Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: April 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel
  • RESTRICTED INSTRUCTIONS IN TRANSACTIONAL EXECUTION
    Publication number: 20180101386
    Abstract: Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions.
    Type: Application
    Filed: December 8, 2017
    Publication date: April 12, 2018
    Inventors: Dan F. Greiner, Christian Jacobi, Timothy J. Slegel