Abstract: A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.

Abstract: A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.

Abstract: A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.

Abstract: A memory module comprising: a plurality of memory devices associated with the module; each of the memory devices being configured in M banks; and a logic circuit for configuring the memory module to operate in a programmable addressing mode; the logic circuit receiving a number of address inputs and a number of bank address signals from a memory controller with the address inputs and bank address input signals corresponding to N bank memory devices; the logic circuit re-mapping at least one of said address inputs as an additional bank address signal to the memory device or at least one of the bank address signals to a different device bank address.

Abstract: A highspeed bus architecture featuring low signal levels, differential sensing, and zero net current over a four wire transmission line cluster. The bus system comprises a system for transmitting n bits of data and includes an encoding system for receiving the n bits of data and outputting m signals wherein the m signals have a zero net current, m transmission lines for carrying the m signals, and a decoding system for receiving the m signals and converting the m signals back into n bits of data, using differential amplifiers.

Abstract: A memory module includes a plurality of memory chips on the module; first logic for configuring the memory module to operate in a selectable mode; second logic for storing initial presence detect (PD) data; and third logic for storing modified PD data that corresponds to a requested mode of operation of the memory module received from a system controller. The system checks the first logic to see if the mode is compatible with the system mode. If not, different PD data is written to and read from the third logic successively until a compatible mode is found or the available PD data is exhausted.

Abstract: A memory module comprising: a plurality of memory devices associated with the module; each of said memory devices being configured in M banks; and a logic circuit for configuring the memory module to operate in a programmable addressing mode; said logic circuit receiving a number of address inputs and a number of bank address signals from a memory controller with said address inputs and bank address input signals corresponding to N bank memory devices; said logic circuit re-mapping at least one of said address inputs as an additional bank address signal to the memory device or at least one of said bank address signals to a different device bank address.

Abstract: A memory module includes a plurality of memory chips on the module; first logic for configuring the memory module to operate in a selectable mode; second logic for storing initial presence detect (PD) data; and third logic for storing modified PD data that corresponds to a requested mode of operation of the memory module received from a system controller.

Abstract: A memory module comprising: a plurality of memory devices associated with the module; each of said memory devices being configured in M banks; and a logic circuit for configuring the memory module to operate in a programmable addressing mode; said logic circuit receiving a number of address inputs and a number of bank address signals from a memory controller with said address inputs and bank address input signals corresponding to N bank memory devices; said logic circuit re-mapping at least one of said address inputs as an additional bank address signal to the memory device.

Abstract: A memory module includes a plurality of memory chips on the module; first logic for configuring the memory module to operate in a selectable mode; second logic for storing initial presence detect (PD) data; and third logic for storing modified PD data that corresponds to a requested mode of operation of the memory module received from a system controller.

Abstract: A packaging assembly for semiconductor memory modules using synchronous clocking signals distributed to each module within a package. The clock distribution network on the assembly is characterized by including a transmission line termination means, preferably a resistor, coupled immediately adjacent to one of the assembly input pins.

Abstract: A memory module configured such that it can be operated as a first memory module such as a (Single In-line Memory Module) SIMM or as a second memory module such as a (Dual In-linc Memory Module) DIMM module without requiring external switching circuitry. This is accomplished by providing a memory module card with a circuit thereon that is designed to emulate a DIMM module when plugged into a DIMM socket as found in the latest computer architectures and to emulate a SIMM module when plugged into a SIMM socket as found in older computer architectures. The memory module is provided with memory devices (DRAMS or SDRAMS) and interconnecting bypass devices (CMOS transistor pairs) mounted thereon.

Abstract: A printed circuit card having first and second circuit units mounted thereon in connection to terminal pads adjacent two card edges, with the first and second circuit units being in connection to each other and to select pads of a first edge such that upon insertion of that edge into a given card socket, both circuit units are enabled, and the circuit units also being in connection to the pads of a second edge such that upon insertion of that edge into a second card socket, only the second circuit unit is enabled. In the preferred embodiment, the card is a memory module card having buffer and memory circuit units designed to cooperate with each other and with either of standard, buffered or unbuffered memory card sockets in a system board in accordance with insertion of a first or second pad edge in one of the card sockets to automatically provide, either combined circuit unit operation, or single circuit operation. The invention is also applicable to clocked register circuits and series pass devices.

Abstract: A dynamically configurable memory adapter is provided for configuring SIMMs in a computer system which employs DIMMs. The adapter includes a plurality of SIMM sockets, a programmable logic device, an EEPROM, a bus controller, and DIP switches. The programmable logic device includes logic for interrogating and configuring serial presence detect data based on a plurality of SIMM characteristics included therein. The serial presence detect data is read by the computer system memory controller during the boot-up process. The dynamically configurable memory adapter also includes direct wiring between the DIMM interface and the SIMMs to thereby allow the SIMMs to directly talk to the memory controller.

Abstract: A method and apparatus are described for providing a human sensorially significant indication of the occurrence of a sequence of error events in an ECC system as they occur over time. Each error indication element is kept activated for a human sensorially significant ("HSS") time interval which is tracked by maintaining a count of refresh pulses received from a memory system. A HSS interval timer includes a D-type flip flop which pulses a binary counter for each refresh operation. The counter, when full, produces a reset signal. An error indication signal from an ECC system is provided to a error condition latch which activates a sensorial error indicator element if the error indication signal is provided to the latch while the memory system is performing a memory read operation. The latch is subsequently reset by the reset signal from the counter after a HSS interval has transpired.

Abstract: A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip.

Abstract: According to the present invention, a computer system and method of operation of the system is provided wherein the computer system has a memory controller which generates first and second RAS signals and Y rows of addresses in memory, and wherein the memory of the system, either as a planar or add-on memory, is configured with Y+1 rows of addresses operable by a single RAS. The system includes logic, preferably which is on an ASIC chip, to convert one of the RAS signals from the memory controller to the high order address bit for the memory rows, thus constituting Y+1 rows of addressable space. The logic also generates a master RAS signal when either RAS generated by the memory controller goes active. The logic also provides for a refresh operation of all of the memory locations during a RAS only refresh operation. This is preferably controlled by a counter in the logic circuit which assures that each row gets refreshed in order when both RASes go LOW for a refresh cycle.

Abstract: A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip.

Abstract: A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip.

Abstract: Reduced specification DRAMs are used in memory assemblies in such a way as to maximize the use of the good cells in the reduced specification DRAM chips. An external memory array is mapped to replace defective memory locations on a real time basis. The major components are (1) a non-volatile storage device, (2) a logic device, and (3) a volatile storage device. The non-volatile storage device, such as an EPROM, EEPROM, or a flash memory chip, is used to retain address information for all memory fails on a given assembly. In simpler implementations, the use of specific combinations of RAM failure types can be used in addition to a logic decode chip, with the raw card identifying to the decode chip the failing address information (via solder jumpers). The logic device is an ASIC or programmable logic device which contains the bit steering logic and timing generation logic to redirect defective RAM addresses to an alternate storage device for all read and write operations.