Abstract: The signal configuration for addressable DRAMs from a system is changed from a signal that actuates a single bank of DRAMs having Y/X row/column addresses actuated by a single RAS, to a signal configuration that provides two RAS signals for two banks of DRAMs having Y-1/X row/column addresses actuated by two RAS signals. This is done by converting the high order address bit from the system to a RAS signal actuated by a system RAS when, and only when, the high order bit is of a given value.

Abstract: A high speed/narrow I/O DRAM device comprises both a data input/output (I/O) port as well as a command port for receiving commands used to control the operations of the DRAM. The command port is defined as input only (i.e., for inputting command data). The present invention comprises multiplexing write data to be written and stored in the DRAM onto the command port with command data packets. The data I/O port can then become dedicated to streaming out seamless data since it no longer needs to flip between input and output data. Even greater bus efficiency can be realized if, during a command packet transfer, data writes to the DRAM are switched back to the data I/O port. With this input port switching protocol, greater bus efficiency and increased memory performance can be realized.

Abstract: According to the preferred embodiment, a method is provided to electronically detect the presence of error correcting memory modules in a computer system in an easy and efficient manner. The method forces an error in the memory system and detects whether there is an error reporting output on the error active line. In the preferred method, the memory refresh for the memory system is turned off for a period of time sufficient to introduce errors in the memory. Then, a read is done while monitoring the error active line. If any bank of memory has an error line active go active during a read, than an error correcting memory module is installed. If not, than a standard memory module is installed.

Abstract: A method and logic circuit are provided which method and logic circuit allow both a CBR and hidden refresh to take place on DRAM's populating SIMM's or DIMM's, wherein both a single system RAS and single system CAS are converted to multiple RAS's and multiple CAS's for normal read/write operation on the DRAM's.