Abstract: A programmable logic device comprising one or more horizontal routing channels, one or more vertical routing channels, and a logic element. Each logic element may be configured to connect between one of the horizontal routing channels and one of the vertical routing channels. The logic element may comprise a logic block cluster and a memory block.

Abstract: A programmable logic device comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first plurality of clock signals in response to (i) one or more input clock signals and (ii) a configuration signal. The second circuit may be configured to generate a second plurality of clock signals in response to (i) said first plurality of clock signals and (ii) said configuration signal. The third circuit may be configured to present a third plurality of clock signals selected from (i) said one or more input clock signals, (ii) said second plurality of clock signals in response to said configuration signal.

Abstract: An apparatus comprising an input/output circuit and a programmable logic device. The input/output circuit may be configured to (i) connect to an end of a bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate said one or more control signals.

Abstract: According to one embodiment, a method for programming a programmable logic device (PLD) may include reading configuration data from a memory device to program a first portion of a PLD to function as a data decompression circuit (304, 308). Compressed configuration data may then be read and decompressed by the first portion and used to program a second portion (310, 312, 315) with a user determined function. A first portion may then be reprogrammed with a user determined function (320, 324).

Abstract: An apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate the control signals.

Abstract: A programmable switch includes at least one or more pass transistors having a control voltage that is greater than the data path reference voltage that is selected by a corresponding pass transistor. The control voltage is provided by a higher voltage power supply than the power supply that provides the data path reference voltage. In one embodiment, the higher voltage supply is a quiet supply that is not loaded with devices that switch during normal operation of the programmable switch such as CMOS devices. In another embodiment, the power supply that provides a voltage to an I/O circuit of the probable switch is the power supply that is utilized to provide the control voltage to the pass transistors. In a particular embodiment, the pass transistors comprise higher voltage tolerant devices than other devices in the programmable device. In a particular embodiment, the higher voltage supply is at least the data path reference voltage plus the threshold voltage of the pass transistors.

Abstract: An apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate the control signals.

Abstract: A programmable logic device comprising a core circuit, a first circuit, a second circuit, and a third circuit. The core circuit may be configured to (i) operate at a first supply voltage, (ii) receive one or more internal input signals, and (iii) generate one or more internal output signals. The first circuit may be configured to generate said first supply voltage in response to a second supply voltage. The second circuit may be configured to (i) operate at a third supply voltage and (ii) generate said one or more internal input signals in response to one or more external input signals. The third circuit may be configured to (i) operate at said third supply voltage and (ii) generate one or more external output signals in response to said one or more internal output signals.

Abstract: A voltage regulator includes a static regulator that provides a static regulated supply output as a reference input to a dynamic regulator to provide a regulated supply voltage. In one embodiment, multiple dynamic regulators are connected to the static regulated supply output of the static regulator. The one or more dynamic regulators dynamically detect when the regulated supply voltage is loaded below a predetermined reference level, and provide extra current in response to prevent the regulated supply voltage from drooping. Since the static regulator is capable of handling large average currents, the dynamic regulator circuit can be smaller than a typical dynamic regulator for an equivalent load. Furthermore, since the dynamic regulator provides transient current requirements, the size of the static regulator may be likewise smaller in size than a typical static regulator for an equivalent load.

Abstract: Architecture, circuitry, and methods are provided for operating a high speed, volatile programmable logic integrated circuit using back-up non-volatile memory cells configured on an integrated circuit separate from the programmable logic integrated circuit. The lower density non-volatile memory cells can be formed on an integrated circuit using fabrication steps similar to those used to form, e.g., EEPROM devices or, more specifically, flash EEPROM devices. The programmable logic integrated circuit includes high density, volatile memory cells integrated with high speed, low density configurable CMOS-based logic. By using two separate processing technologies on two separate and distinct monolithic substrates, and interconnecting the separate integrated circuits on a singular monolithic substrate, the advantages of non-volatility can be combined with a high speed programmable circuit.

Abstract: A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a plurality of routing resources and a programming circuit. Good logic blocks are enabled and fully operational when programmed. Nonfunctional logic blocks are disabled, powered off and invisible to the programming software. Each set of logic blocks has a corresponding routing resource. The routing resource corresponding to an enabled set of logic blocks is capable of being configured to provide input and output data paths for the enabled set of logic blocks. The routing resource corresponding to a disabled set of logic blocks is capable of being configured to bypass the disabled set of the logic blocks. The programming circuit stores the configuration data for the routing resources and is capable of providing the configuration data to a routing resource that corresponds to an enabled set of logic blocks.

Abstract: A voltage source is configured to produce a desired voltage and the desired voltage is applied to a programmable cell coupled to the voltage source. Configuration may be accomplished by loading a register with a programmed voltage value which may be received as a serial data stream through a test access port coupled to the register. For one embodiment, the voltage source may be coupled to a gate of the programmable cell, thus allowing testing of margin voltages of the programmable cell. In a further embodiment, the voltage source may be coupled to a drain of the programmable cell through a load line circuit, thus providing a programmed voltage for the programmable cell. In general then, the programmable voltage source is configurable to provide a voltage to the programmable cell in accordance with a programmed voltage value loaded into the programmable voltage source.

Abstract: The present invention concerns an improved charge pump. The charge pump efficiently charges a voltage signal while reducing its power consumption. The charge pump includes at least one diode configured to receive a voltage signal. Coupled to the diode(s) is at least one capacitive device that is capable of coupling charge onto the diode(s). For one embodiment, the capacitive device provides a constant capacitance to more efficiently charge the voltage signal. The charge pump also includes an oscillating circuit that is capable of providing each capacitive device with an oscillating signal that alternates between a first voltage level and a second voltage level at a predetermined frequency. The oscillating circuit includes an odd number of N inverters coupled in a ring wherein an output of the Nth inverter is coupled to the input of the first inverter.

Abstract: The present invention provides a method and apparatus for high yield improvements in programmable logic devices using redundancy. The present invention concerns a programmable logic device comprising a plurality of routings lines coupled to a plurality of logic blocks when programmed. During programming, a path is routed through the routing lines by programming the selected programmable elements. The selected programmable elements are located at each interconnect point between at least two routing lines or two segments of a routing lines along the path. The programmable elements include at least two interconnect circuits coupled in parallel. The programmable element is successfully programmed when at least one of the interconnect circuits is functional after programming.

Abstract: The present invention concerns an improved charge pump. The charge pump efficiently charges a voltage signal while reducing its power consumption. The charge pump includes at least one diode configured to receive a voltage signal. Coupled to the diode(s) is at least one capacitive device that is capable of coupling charge onto the diode(s). For one embodiment, the capacitive device provides a constant capacitance to more efficiently charge the voltage signal. The charge pump also includes an oscillating circuit that is capable of providing each capacitive device with an oscillating signal that alternates between a first voltage level and a second voltage level at a predetermined frequency. The oscillating circuit includes an odd number of N inverters coupled in a ring wherein an output of the Nth inverter is coupled to the input of the first inverter.

Abstract: The burst mode memory architecture using interleaved memory arrays provides even and odd EPROM arrays with data having even addresses stored in the even array and data having odd addresses stored in the odd array. A control circuit receives an initial address from a memory system controller and then accesses all data from the even and odd arrays within a burst address space containing the initial address. A pair of out-of-phase counters generate even and odd addresses, respectively, for accessing the even and odd arrays. Each counter increments addresses sequentially until a burst address space boundary is reached, then the counters wrap around to a beginning of a burst address space to generate any remaining addresses within a burst address space. The burst mode control circuitry is capable of processing a variety of burst sequencing modes. The burst address space size and the burst sequencing mode are selectable.

Abstract: The present invention concerns an improved charge pump. The charge pump efficiently charges a voltage signal while reducing its power consumption. The charge pump includes at least one diode configured to receive a voltage signal. Coupled to the diode(s) is at least one capacitive device that is capable of coupling charge onto the diode(s). For one embodiment, the capacitive device provides a constant capacitance to more efficiently charge the voltage signal. The charge pump also includes an oscillating circuit that is capable of providing each capacitive device with an oscillating signal that alternates between a first voltage level and a second voltage level at a predetermined frequency. The oscillating circuit includes an odd number of N inverters coupled in a ring wherein an output of the Nth inverter is coupled to the input of the first inverter.

Abstract: The burst mode memory architecture using interleaved memory arrays provides even and odd EPROM arrays with data having even addresses stored in the even array and data having odd addresses stored in the odd array. A control circuit receives an initial address from a memory system controller and then accesses all data from the even and odd arrays within a burst address space containing the initial address. A pair of out-of-phase counters generate even and odd addresses, respectively, for accessing the even and odd arrays. Each counter increments addresses sequentially until a burst address space boundary is reached, then the counters wrap around to a beginning of a burst address space to generate any remaining addresses within a burst address space. The burst mode control circuitry is capable of processing a variety of burst sequencing modes. The burst address space size and the burst sequencing mode are selectable.

Abstract: A programmable circuit apparatus having a programmable circuit and an input/output circuit with a first terminal is provided. The programmable circuit apparatus includes a programming circuit, with a bus junction, for programming the programmable circuit. The programmable circuit apparatus further includes an isolation circuit having an isolation input, coupled to the first terminal, and an isolation output, coupled to the bus junction of the programming circuit. The isolation circuit further has an isolation control gate which can receive a control signal and in response to that signal, the control gate controllably couples the isolation input to the isolation output. The programmable circuit apparatus also includes an apparatus for testing the routing, the programming circuitry, and the programmable circuit with a minimal impact on the performance of the programmable circuit.

Abstract: A pseudo-differential sense amplifier with improved common mode noise rejection is disclosed. The sense amplifier is connected to a memory cell via an array path and generates an output signal indicative of the state of the memory cell. The sense amplifier includes an array load device connected via an array node to the array path, a reference load device connected via a reference node to a reference path, a differential stage having a first input connected to the reference node, a second input connected to the array node and an output generating the output signal. The sense amplifier further includes a balancing device, connected to the reference node, for compensating a change in signal, caused by a noise event, at the array node and, thus reducing a delay in the response of the sense amplifier when a transition in the state of the cell occurs.