Abstract: Memory circuit configuration schemes on multi-drop buses are disclosed. In aspects disclosed herein, an on-die mapping logic is provided in a memory circuit. A memory controller communicates with the on-die mapping logic over a multi-drop bus. The on-die mapping logic is configured to receive a predetermined on-die termination (ODT) value from the memory controller prior to being accessed. In response to receiving the predetermined ODT value, the memory circuit sets on-die termination to the predetermined ODT value and instructs an on-die reference signal generator to generate a predetermined reference signal associated with the predetermined ODT value. The predetermined reference signal provides an optimal reference voltage for implementing a desired equalization setting at the memory circuit, thus aiding in preserving signal integrity. Such improved signal integrity reduces errors in accessing the memory circuit, thus leading to improved efficiency and data throughput on the multi-drop bus.

Abstract: A method for data transmission is described. A signaling speed of operation of an electronic device is determined. A data bus inversion algorithm is selected based on the signaling speed of operation. The selected data bus inversion algorithm is used to encode data. The encoded data and a data bus inversion flag are sent to a receiver over a transmission medium.

Abstract: A source-synchronous system is provided in which a non-uniform interface may exist in a data source endpoint as well as in a data sink endpoint.

Abstract: System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state.

Abstract: A method for data transmission is described. A signaling speed of operation of an electronic device is determined. A data bus inversion algorithm is selected based on the signaling speed of operation. The selected data bus inversion algorithm is used to encode data. The encoded data and a data bus inversion flag are sent to a receiver over a transmission medium.

Abstract: A source-synchronous system is provided in which a non-uniform interface may exist in a data source endpoint as well as in a data sink endpoint.

Abstract: A method for data transmission is described. A signaling speed of operation of an electronic device is determined. A data bus inversion algorithm is selected based on the signaling speed of operation. The selected data bus inversion algorithm is used to encode data. The encoded data and a data bus inversion flag are sent to a receiver over a transmission medium.

Abstract: A source-synchronous system is provided in which a non-uniform interface may exist in a data source endpoint as well as in a data sink endpoint.

Abstract: Systems and methods for frequency control on a bus through superposition are disclosed. In one embodiment, instead of adding pins or increasing the operating frequency of the bus, three signals are placed on lines within the bus using superposition. In this fashion, three bits may be sent over two conductors, effectively obviating the need for an additional pin and effectively increasing the frequency of bit transmission without having to increase the clock speed.

Abstract: One feature pertains to a single data pattern being read from a pattern register located within a memory circuit or device. At least one of the plurality of data patterns is derived from the single data pattern, and the plurality of data patterns may be used in a test and sent to an output driver of the memory circuit. The plurality of data patterns may include a first data pattern and a second data pattern. The first data pattern may be derived from the single data pattern. The second data pattern is one of either a true copy of the single data pattern, an inverse copy of the single data pattern, an all zero bits data pattern, or an all one bits data pattern.

Abstract: Systems and methods for equalizing an output driver circuit based on information from calibration of the output impedance of the driver circuit are disclosed. Settings that result from the calibration are referred to as calibration codes. The output driver circuit includes multiple pull-up elements that are enabled or disabled to produce a desired output impedance when the output is high and multiple pull-down elements that are enabled or disabled to produce the desired output impedance when the output is low. The number of pull-up elements that are enabled and the number of pull-down elements that are enabled is set by calibration. The results of the calibration (i.e., the number of enabled elements for the pull-up and the number of enabled elements for the pull-down) are used to set controls for an amount of pre-emphasis and/or to set controls for output slew rates.

Abstract: System, methods and apparatus are described that facilitate communications circuit design. A first response of a channel to a first signal transmitted through the channel and a second response of the channel to a second signal transmitted through a neighboring channel are determined and a first signal analysis based on the first response and the second response is calculated. A modified second response is determined after modifying the magnitude or timing of the second response to simulate a change in a characteristic of the second signal. A second signal analysis performed using the first response and the modified second response may identify differences in the effects of the second signal and the modified second signal on the first signal. A physical relationship between a pair of connectors of a circuit may be modified based on the magnitude of a scaling factor or phase difference used to obtain the second response.

Abstract: One feature is a method of reading data from a plurality of pattern registers, generating a first output at a mapping register from the read data, generating a second output, different from the first output, at the mapping register from the read data, and generating a multi-level signal using the first and second outputs. In one embodiment, generating the first output is done by adding a first plurality of bits to a second plurality of bits, and generating the second output is done by adding the first plurality of bits to an inverse of the second plurality of bits.

Abstract: Systems and methods for equalizing an output driver circuit based on information from calibration of the output impedance of the driver circuit are disclosed. Settings that result from the calibration are referred to as calibration codes. The output driver circuit includes multiple pull-up elements that are enabled or disabled to produce a desired output impedance when the output is high and multiple pull-down elements that are enabled or disabled to produce the desired output impedance when the output is low. The number of pull-up elements that are enabled and the number of pull-down elements that are enabled is set by calibration. The results of the calibration (i.e., the number of enabled elements for the pull-up and the number of enabled elements for the pull-down) are used to set controls for an amount of pre-emphasis and/or to set controls for output slew rates.

Abstract: System, methods and apparatus are described that facilitate data communications using a single-ended communication link. A method for data communications includes decoupling a direct current component from an alternating current component of a single-ended input signal, biasing the alternating current component with a predetermined bias voltage to obtain a realigned signal, and providing a digital output representative of the input signal by comparing the realigned signal with the predetermined bias voltage. The realigned signal can be compared with the predetermined bias voltage using hysteresis comparison to provide an output signal that switches between logic states compatible with a logic circuit.

Abstract: Electronic devices are adapted to facilitate data encoding for simultaneously limiting both instantaneous current and signal transitions. According to one example, an electronic device may perform a first encoding scheme on a group of data bits to be transmitted on a data bus. The first encoding scheme may be performed based on a number of transitions within the group of data bits for each data channel. A second encoding scheme may also be performed on the group of data bits. The second encoding scheme may be performed based on a number of data bits within the group of data bits for each data channel exhibiting a predetermined state (e.g., a one or a zero). After both encoding scheme are performed on the group of data bits, the encoded data bits may be transmitted over respective data channels of the data bus. Other aspects, embodiments, and features are also included.

Abstract: Memory circuit configuration schemes on multi-drop buses are disclosed. In aspects disclosed herein, an on-die mapping logic is provided in a memory circuit. A memory controller communicates with the on-die mapping logic over a multi-drop bus. The on-die mapping logic is configured to receive a predetermined on-die termination (ODT) value from the memory controller prior to being accessed. In response to receiving the predetermined ODT value, the memory circuit sets on-die termination to the predetermined ODT value and instructs an on-die reference signal generator to generate a predetermined reference signal associated with the predetermined ODT value. The predetermined reference signal provides an optimal reference voltage for implementing a desired equalization setting at the memory circuit, thus aiding in preserving signal integrity. Such improved signal integrity reduces errors in accessing the memory circuit, thus leading to improved efficiency and data throughput on the multi-drop bus.

Abstract: A data bus is split into partitions and encoding is independently applied to data transmitted over each bus partition to improve power and/or throughput efficiency. The encoding can be data bus inversion or any other suitable type of encoding. An encoding indicator symbol transmitted in conjunction with the data indicates which bus partition is encoded, if any. In some implementations, encoding is selectively applied to each bus partition during each data transfer cycle of a parallel data bus. In some implementation, the encoding indicator symbol is a multi-level signal where each level of the multi-level signal represents at least two bits of information indicative of, for a corresponding bus partition, whether encoding is applied to the data to be transmitted over the bus partition. Advantageously, the encoding indicator symbol can be transmitted over a single, dedicated bus line.

Abstract: High-speed data links between a processor and off-chip DRAM utilizes pulse-amplitude-modulation (PAM) signaling to increase data rate for a given bandwidth and resource budget in SoCs. However, the termination resistor used in the transmission line interface between processor and DRAM consumes large amounts of power during PAM signaling. By adding a biasing source between Ground and the termination resistor, the “floor voltage” that the termination resistor uses as a reference for determining signaling levels may be raised. Raising the floor voltage reduces the amount of voltage across the termination resistor and reduces power consumption accordingly. The biasing source is adjusted to various increments of the maximum amplitude of the PAM signaling. A floor voltage of one-half of the maximum amplitude of PAM signaling produces minimum power consumption in the receiver.

Abstract: High-speed data links between a processor and off-chip DRAM utilizes pulse-amplitude-modulation (PAM) signaling to increase data rate for a given bandwidth and resource budget in SoCs. However, the termination resistor used in the transmission line interface between processor and DRAM consumes large amounts of power during PAM signaling. By adding a biasing source between Ground and the termination resistor, the “floor voltage” that the termination resistor uses as a reference for determining signaling levels may be raised. Raising the floor voltage reduces the amount of voltage across the termination resistor and reduces power consumption accordingly. The biasing source is adjusted to various increments of the maximum amplitude of the PAM signaling. A floor voltage of one-half of the maximum amplitude of PAM signaling produces minimum power consumption in the receiver.