Patents by Inventor Timothy Mowry Hollis

Timothy Mowry Hollis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190287575
    Abstract: Various embodiments, disclosed herein, include apparatus and methods to provide separate regulated voltages to an electronic device. Multiple voltage regulators can be provided with phase alignment circuitry coupled to the multiple voltage regulators. The multiple voltage regulators can be structured with each voltage regulator having an output separate from the output of the other voltage regulators. The phase alignment circuitry can provide for relative phases among voltage regulator ripples at the output pins of the multiple voltage regulators to be maintained at a certain relationship. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: May 31, 2019
    Publication date: September 19, 2019
    Inventor: Timothy Mowry Hollis
  • Patent number: 10347303
    Abstract: Various embodiments, disclosed herein, include apparatus and methods to provide separate regulated voltages to an electronic device. Multiple voltage regulators can be provided with phase alignment circuitry coupled to the multiple voltage regulators. The multiple voltage regulators can be structured with each voltage regulator having an output separate from the output of the other voltage regulators. The phase alignment circuitry can provide for relative phases among voltage regulator ripples at the output pins of the multiple voltage regulators to be maintained at a certain relationship. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Timothy Mowry Hollis
  • Patent number: 10339075
    Abstract: A computing system including multiple integrated circuit memory devices is described. One or more command and address buses are connected to the memory devices to transmit command and address signals to each memory device. Multiple clock lines are connected to the multiple memory devices in a tree structure to transmit multiple clock signals to these memory devices. The tree structure allows each distributed clock signal to be individually trained such that the multiple clock signals provide each memory device with a clock signal that is temporally aligned with the command and address signals as received by that memory device.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Roy E. Greeff, George Pax, Timothy Mowry Hollis
  • Publication number: 20190138388
    Abstract: Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated circuits (ICs) is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional RAM ICs, and accordingly the RAM ICs can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified RAM IC's and a traditional memory controller, additionally contains DBI encoding and decoding circuitry. In such a system, data is DBI encoded and at least one DBI bit issued when writing to the modified RAM ICs. The RAM ICs in turn store the DBI bit(s) with the encoded data. When the encoded data is read from the modified RAM ICs, it is transmitted across the bus in its encoded state along with the DBI bit(s). The logic integrated circuit then decodes the data using the DBI bit(s) to return it to its original state.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 9, 2019
    Inventor: Timothy Mowry Hollis
  • Publication number: 20190116070
    Abstract: Various embodiments, disclosed herein, can include apparatus and methods to characterize taps of a decision feedback equalizer of a data receiver. In characterizing the taps of the decision feedback equalizer of the data receiver, signal can be transmitted to the data receiver and the received data can be iteratively sampled at an output of the decision feedback equalizer. The sampling can include stepping a sample time relative to arrival of the received data and stepping a reference voltage level to which the received data is compared. Values of the sampled data can be compared with known correct values and such measurements can be used to characterize the taps. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: November 27, 2018
    Publication date: April 18, 2019
    Inventor: Timothy Mowry Hollis
  • Publication number: 20190064871
    Abstract: A computing system including multiple integrated circuit memory devices is described. One or more command and address buses are connected to the memory devices to transmit command and address signals to each memory device. Multiple clock lines are connected to the multiple memory devices in a tree structure to transmit multiple clock signals to these memory devices. The tree structure allows each distributed clock signal to be individually trained such that the multiple clock signals provide each memory device with a clock signal that is temporally aligned with the command and address signals as received by that memory device.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Roy E. Greeff, George Pax, Timothy Mowry Hollis
  • Publication number: 20190043538
    Abstract: Various embodiments, disclosed herein, include apparatus and methods to provide separate regulated voltages to an electronic device. Multiple voltage regulators can be provided with phase alignment circuitry coupled to the multiple voltage regulators. The multiple voltage regulators can be structured with each voltage regulator having an output separate from the output of the other voltage regulators. The phase alignment circuitry can provide for relative phases among voltage regulator ripples at the output pins of the multiple voltage regulators to be maintained at a certain relationship. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: August 1, 2017
    Publication date: February 7, 2019
    Inventor: Timothy Mowry Hollis
  • Patent number: 10164805
    Abstract: Various embodiments, disclosed herein, can include apparatus and methods to characterize taps of a decision feedback equalizer of a data receiver. In characterizing the taps of the decision feedback equalizer of the data receiver, a signal can be transmitted to the data receiver and the received data can be iteratively sampled at an output of the decision feedback equalizer. The sampling can include stepping a sample time relative to arrival of the received data and stepping a reference voltage level to which the received data is compared. Values of the sampled data can be compared with known correct values and such measurements can be used to characterize the taps. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Timothy Mowry Hollis
  • Publication number: 20180232289
    Abstract: Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners.
    Type: Application
    Filed: April 16, 2018
    Publication date: August 16, 2018
    Inventor: Timothy Mowry Hollis
  • Patent number: 9921993
    Abstract: Memory circuit configuration schemes on multi-drop buses are disclosed. In aspects disclosed herein, an on-die mapping logic is provided in a memory circuit. A memory controller communicates with the on-die mapping logic over a multi-drop bus. The on-die mapping logic is configured to receive a predetermined on-die termination (ODT) value from the memory controller prior to being accessed. In response to receiving the predetermined ODT value, the memory circuit sets on-die termination to the predetermined ODT value and instructs an on-die reference signal generator to generate a predetermined reference signal associated with the predetermined ODT value. The predetermined reference signal provides an optimal reference voltage for implementing a desired equalization setting at the memory circuit, thus aiding in preserving signal integrity. Such improved signal integrity reduces errors in accessing the memory circuit, thus leading to improved efficiency and data throughput on the multi-drop bus.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: March 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Timothy Mowry Hollis
  • Patent number: 9798693
    Abstract: A method for data transmission is described. A signaling speed of operation of an electronic device is determined. A data bus inversion algorithm is selected based on the signaling speed of operation. The selected data bus inversion algorithm is used to encode data. The encoded data and a data bus inversion flag are sent to a receiver over a transmission medium.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: October 24, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Timothy Mowry Hollis
  • Patent number: 9773542
    Abstract: A source-synchronous system is provided in which a non-uniform interface may exist in a data source endpoint as well as in a data sink endpoint.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: September 26, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Timothy Mowry Hollis, Michael Joseph Brunolli
  • Patent number: 9621385
    Abstract: System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: April 11, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Timothy Mowry Hollis
  • Publication number: 20170075854
    Abstract: A method for data transmission is described. A signaling speed of operation of an electronic device is determined. A data bus inversion algorithm is selected based on the signaling speed of operation. The selected data bus inversion algorithm is used to encode data. The encoded data and a data bus inversion flag are sent to a receiver over a transmission medium.
    Type: Application
    Filed: November 28, 2016
    Publication date: March 16, 2017
    Inventor: Timothy Mowry Hollis
  • Publication number: 20170062042
    Abstract: A source-synchronous system is provided in which a non-uniform interface may exist in a data source endpoint as well as in a data sink endpoint.
    Type: Application
    Filed: November 10, 2016
    Publication date: March 2, 2017
    Inventors: Timothy Mowry Hollis, Michael Joseph Brunolli
  • Patent number: 9529749
    Abstract: A method for data transmission is described. A signaling speed of operation of an electronic device is determined. A data bus inversion algorithm is selected based on the signaling speed of operation. The selected data bus inversion algorithm is used to encode data. The encoded data and a data bus inversion flag are sent to a receiver over a transmission medium.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: December 27, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Timothy Mowry Hollis
  • Patent number: 9524763
    Abstract: A source-synchronous system is provided in which a non-uniform interface may exist in a data source endpoint as well as in a data sink endpoint.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: December 20, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Timothy Mowry Hollis, Michael Joseph Brunolli
  • Patent number: 9519604
    Abstract: Systems and methods for frequency control on a bus through superposition are disclosed. In one embodiment, instead of adding pins or increasing the operating frequency of the bus, three signals are placed on lines within the bus using superposition. In this fashion, three bits may be sent over two conductors, effectively obviating the need for an additional pin and effectively increasing the frequency of bit transmission without having to increase the clock speed.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: December 13, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Timothy Mowry Hollis
  • Patent number: 9443614
    Abstract: One feature pertains to a single data pattern being read from a pattern register located within a memory circuit or device. At least one of the plurality of data patterns is derived from the single data pattern, and the plurality of data patterns may be used in a test and sent to an output driver of the memory circuit. The plurality of data patterns may include a first data pattern and a second data pattern. The first data pattern may be derived from the single data pattern. The second data pattern is one of either a true copy of the single data pattern, an inverse copy of the single data pattern, an all zero bits data pattern, or an all one bits data pattern.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: September 13, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Timothy Mowry Hollis
  • Patent number: 9337807
    Abstract: Systems and methods for equalizing an output driver circuit based on information from calibration of the output impedance of the driver circuit are disclosed. Settings that result from the calibration are referred to as calibration codes. The output driver circuit includes multiple pull-up elements that are enabled or disabled to produce a desired output impedance when the output is high and multiple pull-down elements that are enabled or disabled to produce the desired output impedance when the output is low. The number of pull-up elements that are enabled and the number of pull-down elements that are enabled is set by calibration. The results of the calibration (i.e., the number of enabled elements for the pull-up and the number of enabled elements for the pull-down) are used to set controls for an amount of pre-emphasis and/or to set controls for output slew rates.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: May 10, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Timothy Mowry Hollis, Thomas Clark Bryan, Mark Wayland