Abstract: Disclosed is a transistor having a base, a substrate, and a collector between the substrate and the base. The collector has a first region of a first thickness under the base and is made up of a first dopant type having a substantially constant doping concentration across the first thickness. A second region with a second thickness under the first region is made up of a second dopant type that is different from the first dopant type and has a substantially constant doping concentration across the second thickness. A third region with a third thickness under the second region is made up of the second dopant type with a graded doping concentration that is a function of increasing distance from the second region through the third thickness. An emitter is located over the base opposite the collector.

Abstract: Disclosed is a transistor having a base, a substrate, and a collector between the substrate and the base. The collector has a first region of a first thickness under the base and is made up of a first dopant type having a substantially constant doping concentration across the first thickness. A second region with a second thickness under the first region is made up of a second dopant type that is different from the first dopant type and has a substantially constant doping concentration across the second thickness. A third region with a third thickness under the second region is made up of the second dopant type with a graded doping concentration that is a function of increasing distance from the second region through the third thickness. An emitter is located over the base opposite the collector.

Abstract: A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.

Abstract: Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common.

Abstract: A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.

Abstract: A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.

Abstract: Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device includes a diffusion control layer as part of an emitter epitaxial structure. The IC device may utilize a common metallization scheme to simultaneously form an emitter contact and a base contact. Other embodiments may also be described and/or claimed.

Abstract: A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device includes a diffusion control layer as part of an emitter epitaxial structure. The IC device may utilize a common metallization scheme to simultaneously form an emitter contact and a base contact. Other embodiments may also be described and/or claimed.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device includes a diffusion control layer as part of an emitter epitaxial structure. The IC device may utilize a common metallization scheme to simultaneously form an emitter contact and a base contact. Other embodiments may also be described and/or claimed.

Abstract: Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common.

Abstract: Various embodiments provide an electrostatic discharge (ESD) protection device. The ESD protection device may include a subcollector, collector, base, and emitter formed in layers on top of one another. The emitter may include a different semiconductor than a semiconductor included in the base to form a heterojunction. The ESD protection device may include a collector contact disposed on the subcollector and an emitter contact disposed on the emitter. The ESD protection device may be a two-terminal device, with no conductive base contact coupled with the base.

Abstract: Various embodiments provide an electrostatic discharge (ESD) protection device. The ESD protection device may include a subcollector, collector, base, and emitter formed in layers on top of one another. The emitter may include a different semiconductor than a semiconductor included in the base to form a heterojunction. The ESD protection device may include a collector contact disposed on the subcollector and an emitter contact disposed on the emitter. The ESD protection device may be a two-terminal device, with no conductive base contact coupled with the base.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device includes a diffusion control layer as part of an emitter epitaxial structure. The IC device may utilize a common metallization scheme to simultaneously form an emitter contact and a base contact. Other embodiments may also be described and/or claimed.

Abstract: A bipolar transistor includes a passivating layer of material 40 in the base structure 42 that serves to cover the extrinsic base region of the transistor. The passivating layer 40 is formed of a material having a wider bandgap than the base layer 44, and is heavily doped with the same doping type (n or p) as the base layer. The invention is advantageous in that the base contacts 48 of the device are made directly to the passivating layer 40 and are not in direct contact with the base layer 44. This eliminates the need for alloyed contacts and the concomitant reliability problems associated with spiking contacts. In addition, the invention is completely compatible with self-aligned production techniques.

Abstract: A method of etching Group III-V semiconductor materials wherein a plasma of methane, hydrogen and freon is provided in a reactive ion etching chamber having a semiconductor substrate therein and maintaining the substrate to be etched at an elevated temperature of about 100.degree. C. in vacuum conditions of from about 1 to about 100 milliTorr. The temperature range utilized herein is substantially higher than the temperatures used in prior art reactive ion etching of Group III-V compositions and provides substantially superior results as compared with tests of reactive ion etching using all materials and parameters used herein except that the temperature of the substrate being etched was about 34.degree. C. The amount of methane can be from a flow rate of about 5 zero to about 50 SCCM and preferably about 10 SCCM, the flow rate of hydrogen can be from about zero to about 40 SCCM and preferably about 30 SCCM and the flow rate of freon can be from about 5 to about 50 SCCM and preferably about 17 SCCM.

Abstract: Generally, and in one form of the invention a method for making a heterojunction bipolar transistor comprising the steps of forming a compound semiconductor material structure comprised of a plurality of layers, wherein at least one of the plurality of layers is comprised of a first material (e.g. GaAs 36) and at least one of the remaining of the plurality of layers is comprised of a second material (e.g. AlGaAs 32); and etching the layers comprised of the first material with an etchant that does not appreciably etch the layers of the second material is disclosed. A surprising aspect of this invention is that no additional etch stop layer was added in the material structure. Etchants were found that stop on the wide band gap emitter layer (e.g. AlGaAs) usually found in heterojunction bipolar transistors despite the similarity of the materials.

Abstract: A bipolar transistor includes a passivating layer of material 40 in the base structure 42 that serves to cover the extrinsic base region of the transistor. The passivating layer 40 is formed of a material having a wider bandgap than the base layer 44, and is heavily doped with the same doping type (n or p) as the base layer. The invention is advantageous in that the base contacts 48 of the device are made directly to the passivating layer 40 and are not in direct contact with the base layer 44. This eliminates the need for alloyed contacts and the concomitant reliability problems associated with spiking contacts. In addition, the invention is completely compatible with self-aligned production techniques.

Abstract: A method of etching Group III-V semiconductor materials wherein a plasma of methane, hydrogen and freon is provided in a reactive ion etching chamber having a semiconductor substrate therein and maintaining the substrate to be etched at an elevated temperature of about 100.degree. C. in vacuum conditions of from about 1 to about 100 milliTorr. The temperature range utilized herein is substantially higher than the temperatures used in prior art reactive ion etching of Group III-V compositions and provides substantially superior results as compared with tests of reactive ion etching using all materials and parameters used herein except that the temperature of the substrate being etched was about 34.degree. C. The amount of methane can be from a flow rate of about 5 zero to about 50 SCCM and preferably about 10 SCCM, the flow rate of hydrogen can be from about zero to about 40 SCCM and preferably about 30 SCCM and the flow rate of freon can be from about 5 to about 50 SCCM and preferably about 17 SCCM.