Patents by Inventor Timothy Thurgate
Timothy Thurgate has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11257675Abstract: A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.Type: GrantFiled: June 26, 2019Date of Patent: February 22, 2022Assignee: Cypress Semiconductor CorporationInventors: Shenqing Fang, Timothy Thurgate, Kuo Tung Chang
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Patent number: 10644016Abstract: A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.Type: GrantFiled: October 30, 2014Date of Patent: May 5, 2020Assignee: Cypress Semiconductor CorporationInventors: Kuo Tung Chang, Shenqing Fang, Timothy Thurgate
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Publication number: 20190385853Abstract: A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.Type: ApplicationFiled: June 26, 2019Publication date: December 19, 2019Applicant: Cypress Semiconductor CorporationInventors: Shenqing Fang, Timothy Thurgate, Kuo Tung Chang
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Patent number: 9559216Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a tunneling insulating layer and disposed between the first region and the second region.Type: GrantFiled: June 6, 2011Date of Patent: January 31, 2017Assignee: MICRON TECHNOLOGY, INC.Inventors: Srinivasa Rao Banna, Michael A. Van Buskirk, Timothy Thurgate
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Patent number: 9524971Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: GrantFiled: February 5, 2015Date of Patent: December 20, 2016Inventors: Srinivasa R. Banna, Michael A. van Buskirk, Timothy Thurgate
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Publication number: 20160126250Abstract: A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.Type: ApplicationFiled: October 30, 2014Publication date: May 5, 2016Applicant: Spansion LLCInventors: Kuo Tung CHANG, Shenqing Fang, Timothy Thurgate
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Patent number: 9263133Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.Type: GrantFiled: August 30, 2013Date of Patent: February 16, 2016Assignee: MICRON TECHNOLOGY, INC.Inventors: Srinivasa R. Banna, Michael A. Van Bushkirk, Timothy Thurgate
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Publication number: 20150333188Abstract: A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.Type: ApplicationFiled: May 15, 2014Publication date: November 19, 2015Applicant: Spansion LLCInventors: Shenqing FANG, Timothy Thurgate, Kuo Tung Chang
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Publication number: 20150171100Abstract: A process for forming tilted edge wordline implants is disclosed. The process includes forming a first drain implant in a substrate, forming a first tilted implant in a substrate adjacent a first edge wordline to supplement said first drain implant where the first tilted implant is provided at a tilt angle from a first direction and forming a second tilted implant in the substrate adjacent a second edge wordline to supplement another first drain implant where the second tilted implant is provided at a tilt angle from a second direction. A second drain implant is formed in the substrate.Type: ApplicationFiled: December 17, 2013Publication date: June 18, 2015Applicant: Spansion LLCInventors: Timothy THURGATE, Yu SUN, Chun CHEN
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Publication number: 20150155285Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: ApplicationFiled: February 5, 2015Publication date: June 4, 2015Applicant: Micron Technology, Inc.Inventors: Srinivasa R. BANNA, Michael A. VAN BUSKIRK, Timothy THURGATE
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Patent number: 9019759Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: GrantFiled: October 1, 2013Date of Patent: April 28, 2015Assignee: Micron Technology, Inc.Inventors: Srinivasa R. Banna, Michael A. Van Buskirk, Timothy Thurgate
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Publication number: 20140029360Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: ApplicationFiled: October 1, 2013Publication date: January 30, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Srinivasa R. BANNA, Michael A. VAN BUSKIRK, Timothy THURGATE
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Publication number: 20140003144Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.Type: ApplicationFiled: August 30, 2013Publication date: January 2, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Srinivasa R. BANNA, Michael A. VAN BUSKIRK, Timothy THURGATE
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Patent number: 8547738Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.Type: GrantFiled: March 14, 2011Date of Patent: October 1, 2013Assignee: Micron Technology, Inc.Inventors: Srinivasa Rao Banna, Michael A. Van Buskirk, Timothy Thurgate
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Patent number: 8531878Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.Type: GrantFiled: May 17, 2011Date of Patent: September 10, 2013Assignee: Micron Technology, Inc.Inventors: Srinivasa Rao Banna, Michael A. Van Buskirk, Timothy Thurgate
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Publication number: 20130228851Abstract: A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.Type: ApplicationFiled: April 8, 2013Publication date: September 5, 2013Applicant: SPANSION LLCInventors: Rinji Sugino, Timothy Thurgate, Jean Yee-Mei Yang, Michael Brennan
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Patent number: 8415734Abstract: A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.Type: GrantFiled: December 7, 2006Date of Patent: April 9, 2013Assignee: Spansion LLCInventors: Rinji Sugino, Timothy Thurgate, Jean Yee-Mei Yang, Michael Brennan
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Patent number: 8409952Abstract: A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.Type: GrantFiled: April 14, 2008Date of Patent: April 2, 2013Assignee: Spansion LLCInventors: Suketu Arun Parikh, Olov B. Karlsson, Yun Sun, Shankar Sinha, Timothy Thurgate
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Publication number: 20120307568Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a tunneling insulating layer and disposed between the first region and the second region.Type: ApplicationFiled: June 6, 2011Publication date: December 6, 2012Applicant: Micron Technology, Inc.Inventors: Srinivasa Rao Banna, Michael A. Van Buskirk, Timothy Thurgate
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Publication number: 20120294083Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.Type: ApplicationFiled: May 17, 2011Publication date: November 22, 2012Applicant: Micron Technology, Inc.Inventors: Srinivasa Rao Banna, Michael A. Van Buskirk, Timothy Thurgate