Abstract: An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second memory device are automatically retrieved and provided responsive to the request. As an example, the memory device may be a cache and the second memory device may be main memory for the computing system.

Abstract: A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. The self-test circuitry includes an AC self-test controller and a clock splitter. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock.

Abstract: A dynamic arbitration controller includes components for reading current state information as well as records of known arbitration states which may cause a deadlock condition, comparing the current state to the records of known arbitration states and resolving deadlock conditions during arbitration. The dynamic arbitration controller may include circuits for storing and retrieving information related to the arbitration. The dynamic arbitration controller may be implemented as a circuit design or as a computer program product stored on machine readable media.

Abstract: A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. The self-test circuitry includes an AC self-test controller and a clock splitter. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock.

Abstract: A method and system for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation are provided. The method includes applying a long data capture pulse to a first test register in response to the system clock, applying an at speed data launch pulse to the first test register in response to the system clock, inputting the data from the first register to a logic path in response to applying the at speed data launch pulse to the first test register, applying an at speed data capture pulse to a second test register in response to the system clock, inputting the logic path output to the second test register in response to applying the at speed data capture pulse to the second test register, and applying a long data launch pulse to the second test register in response to the system clock.

Abstract: An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second memory device are automatically retrieved and provided responsive to the request. As an example, the memory device may be a cache and the second memory device may be main memory for the computing system.

Abstract: An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second memory device are automatically retrieved and provided responsive to the request. As an example, the memory device may be a cache and the second memory device may be main memory for the computing system.

Abstract: A dynamic arbitration controller includes components for reading current state information as well as records of known arbitration states which may cause a deadlock condition, comparing the current state to the records of known arbitration states and resolving deadlock conditions during arbitration. The dynamic arbitration controller may include circuits for storing and retrieving information related to the arbitration. The dynamic arbitration controller may be implemented as a circuit design or as a computer program product stored on machine readable media.

Abstract: A method of writing to cache including initiating a write operation to a cache. In a first operational mode, the presence or absence of a write miss is detected and if a write miss is absent, writing data to the cache and if a write miss is present, retrieving the data from a further memory and writing the data to the cache based on least recently used logic. In a second operational mode, the cache is placed in a memory mode and the data is written to the cache based on an address regardless of whether a write miss is present or absent.

Abstract: An exemplary embodiment of the present invention is a method for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation. The method comprises applying a long data capture pulse to a first test register in response to said system clock. An at speed data launch pulse is applied to the first test register in response to said system clock. The data from the first register is input to a logic path in response to applying the at speed data launch pulse to the first test register. An at speed data capture pulse is applied to a second test register in response to the system clock. The output from the logic path is input to the second test register in response to applying the at speed data capture pulse to the second test register. A long data launch pulse is applied to the second test register in response to the system clock. An additional embodiment includes a system for performing AC self-test on an integrated circuit that includes a system clock.

Abstract: A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.

Abstract: A method for performing AC self-test on an integrated circuit, including a system clock for use during normal operation. The method includes applying a long data capture pulse to a first test register in response to the system clock, and further applying at an speed data launch pulse to the first test register in response to the system clock. Inputting the data from the first register to a logic path in response to applying the at speed data launch pulse to the first test register. Applying at speed data capture pulse to a second test register in response to the system clock. Inputting the output from the logic path to the second test register in response to applying the at speed data capture pulse to the second register. Applying a long data launch pulse to the second test register in response to the system clock.

Abstract: An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second memory device are automatically retrieved and provided responsive to the request. As an example, the memory device may be a cache and the second memory device may be main memory for the computing system.

Abstract: A method is disclosed for instructing a computing system to allocate a trace array from an original cache memory, where the method includes dividing the original cache memory into a reduced-size cache memory and a trace array, permitting storage of trace signal data into the trace array, and permitting retrieval of the trace signal data from the trace array.

Abstract: A system and method for generating random noise for use in testing electronic devices comprises a first random pattern generator circuit for generating first sets of random bit pattern signals; one or more delay devices each receiving a trigger input signal and a random bit pattern signal set for generating in response a respective delay output signal, each delay output signal being delayed in time with respect to a respective trigger signal, a delay time being determined by the bit pattern set received; and, an oscillator circuit device associated with a respective one or more delay devices for receiving a respective delay output signal therefrom and generating a respective oscillating signal, each oscillator signal generated being used to generate artificial random noise for emulating a real noise environment in an electronic device.

Abstract: A method of writing to cache including initiating a write operation to a cache. In a first operational mode, the presence or absence of a write miss is detected and if a write miss is absent, writing data to the cache and if a write miss is present, retrieving the data from a further memory and writing the data to the cache based on least recently used logic. In a second operational mode, the cache is placed in a memory mode and the data is written to the cache based on an address regardless of whether a write miss is present or absent.

Abstract: A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.

Abstract: An exemplary embodiment of the present invention is a method for transmitting data among processors over a plurality of parallel data lines and a clock signal line. A receiver processor receives both data and a clock signal from a sender processor. At the receiver processor a bit of the data is phased aligned with the transmitted clock signal. The phase aligning includes selecting a data phase from a plurality of data phases in a delay chain and then adjusting the selected data phase to compensate for a round-off error. Additional embodiments include a system and storage medium for transmitting data among processors over a plurality of parallel data lines and a clock signal line.

Abstract: A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.

Abstract: An exemplary embodiment of the present invention is a method for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation. The method comprises applying a long data capture pulse to a first test register in response to said system clock. An at speed data launch pulse is applied to the first test register in response to said system clock. The data from the first register is input to a logic path in response to applying the at speed data launch pulse to the first test register. An at speed data capture pulse is applied to a second test register in response to the system clock. The output from the logic path is input to the second test register in response to applying the at speed data capture pulse to the second test register. A long data launch pulse is applied to the second test register in response to the system clock. An additional embodiment includes a system for performing AC self-test on an integrated circuit that includes a system clock.