Patents by Inventor Tin-Chee Lo
Tin-Chee Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6594196Abstract: A multi-port memory array is associated with wordlines and bit-lines to perform data read/write operation and has multi-port memory cells each of which includes multiple ports through which the wordlines and bit-lines are provided, multiple transistor devices each of which corresponds to each of the multiple ports and is coupled to a wordline and a bit-line through a corresponding port, each transistor device being gated by a wordline and having a conduction path of which a first end is connected to a bit-line, and a charge storage device commonly connected to a second end of a conduction path of each of the transistor devices, where the charge storage device is charged when any of the plurality of transistor devices is activated.Type: GrantFiled: November 29, 2000Date of Patent: July 15, 2003Assignee: International Business Machines CorporationInventors: Louis L Hsu, Tin-chee Lo, Li-Kong Wang
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Publication number: 20030088738Abstract: A method is disclosed for instructing a computing system to allocate a trace array from an original cache memory, where the method includes dividing the original cache memory into a reduced-size cache memory and a trace array, permitting storage of trace signal data into the trace array, and permitting retrieval of the trace signal data from the trace array.Type: ApplicationFiled: November 2, 2001Publication date: May 8, 2003Inventors: David B. Fox, Joseph M. Hoke, Tin-Chee Lo
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Publication number: 20030023934Abstract: A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.Type: ApplicationFiled: July 30, 2001Publication date: January 30, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tin-chee Lo, Yuk-Ming Ng, Anil S. Keste
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Publication number: 20030023891Abstract: An exemplary embodiment of the present invention is a method for transmitting data among processors over a plurality of parallel data lines and a clock signal line. A receiver processor receives both data and a clock signal from a sender processor. At the receiver processor a bit of the data is phased aligned with the transmitted clock signal. The phase aligning includes selecting a data phase from a plurality of data phases in a delay chain and then adjusting the selected data phase to compensate for a round-off error. Additional embodiments include a system and storage medium for transmitting data among processors over a plurality of parallel data lines and a clock signal line.Type: ApplicationFiled: July 30, 2001Publication date: January 30, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph Michael Hoke, Frank D. Ferraiolo, Tin-Chee Lo, John Michael Yarolin
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Publication number: 20030009721Abstract: A method and system for background ECC scrubbing, i.e., checking and correcting scheme, for a memory array are provided which do not affect normal system operation of the memory array and do not add additional time delay to the data flow path, especially a data output flow path. Unlike the prior art, an ECC decoder circuit block is placed outside a critical data output path of a memory array. A data refresh path is provided to periodically pull the data out from the memory array via the ECC decoder circuit block for checking and correcting the data. The outgoing data in response to a read command does not suffer any time delay caused by the ECC checking and correcting scheme, since the data are not read out via the ECC decoder circuit block. Any hard errors are corrected by at least one redundancy circuit.Type: ApplicationFiled: July 6, 2001Publication date: January 9, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis L. Hsu, Li-Kong Wang, Tin-Chee Lo, Chorng-Lii Hwang
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Publication number: 20020120898Abstract: A system and method for generating random noise for use in testing electronic devices comprises a first random pattern generator circuit for generating first sets of random bit pattern signals; one or more delay devices each receiving a trigger input signal and a random bit pattern signal set for generating in response a respective delay output signal, each delay output signal being delayed in time with respect to a respective trigger signal, a delay time being determined by the bit pattern set received; and, an oscillator circuit device associated with a respective one or more delay devices for receiving a respective delay output signal therefrom and generating a respective oscillating signal, each oscillator signal generated being used to generate artificial random noise for emulating a real noise environment in an electronic device.Type: ApplicationFiled: February 28, 2001Publication date: August 29, 2002Applicant: International Business Machines CorporatonInventors: Howard H. Chen, Li-Kong Wang, Louis L. Hsu, Sang H. Dhong, Tin-chee Lo
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Publication number: 20020065997Abstract: A multi-port memory array is associated with wordlines and bit-lines to perform data read/write operation and has multi-port memory cells each of which includes multiple ports through which the wordlines and bit-lines are provided, multiple transistor devices each of which corresponds to each of the multiple ports and is coupled to a wordline and a bit-line through a corresponding port, each transistor device being gated by a wordline and having a conduction path of which a first end is connected to a bit-line, and a charge storage device commonly connected to a second end of a conduction path of each of the transistor devices, where the charge storage device is charged when any of the plurality of transistor devices is activated.Type: ApplicationFiled: November 29, 2000Publication date: May 30, 2002Inventors: Louis L. Hsu, Tin-Chee Lo, Li-Kong Wang
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Patent number: 5970052Abstract: A method for dynamic bandwidth testing of a link between two computer subsystems useful for determining the amount of data which can be buffered in a transmission line by delay, in which at each end of the line circuit modules are provided to couple the subsystem by a bi-directional multi-bit (BiDi) link, and providing within each said circuit module a built-in circuit and logic for dynamic transmission characterization and test of a said BiDi link between computer subsystems using built-in characterization logic macros, and during a test mode, switching said said built-in circuit and logic to test mode and using the test mode to characterize the link performance, and after the completion of characterization, the switching built-in characterization logic macros back to a normal system mode after programmatically setting timing parameters for the BiDi link to ensure safe operation of data transfer before the BiDi link is switched to system mode.Type: GrantFiled: September 19, 1997Date of Patent: October 19, 1999Assignee: International Business Machines CorporationInventors: Tin-Chee Lo, George A. Katopis, Timothy Gerard McNamara, David Allan Webber, Joseph L. Braun, Paul R. Turgeon
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Patent number: 5907671Abstract: A fault tolerant circuit having improved error correction and detection properties takes advantage of two distinct forms of information redundancy: modular redundancy and parity check bit redundancy, in a cooperative fashion. In particular, it is shown that simple majority voting logic circuits, when employed in the subject environment, provide an easily realized mechanism for error correction and error detection. This results in an extremely fault tolerant information system.Type: GrantFiled: September 23, 1996Date of Patent: May 25, 1999Assignee: International Business Machines CorporationInventors: Chin-Long Chen, Canh Xuan Le, Tin-Chee Lo, Arnold Weinberger
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Patent number: 5822338Abstract: Directory compare and ECC logic which is interfaced with the array's static and dynamic outputs for the ECC-compare path of a cache directory, using a three-output array providing a static output and a pair of complementary dynamic outputs. The static output is useed by the compare logic for a directory compare. The pair of complementary dynamic outputs provide dynamic signals (t and f) to drive the ECC logic only as ECC logic complementary signals which are coupled to drive a DCVS (Dynamic Cascode Voltage Switch) syndrome generator circuit. The static output signal performs compare-then-correct processing. The dynamic signals of each bit emanating from array are ECC checked but the static signal is not. The static signal is consistent with the t dynamic signal.Type: GrantFiled: January 28, 1998Date of Patent: October 13, 1998Assignee: International Business Machines CorporationInventor: Tin-Chee Lo
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Patent number: 5805789Abstract: Computer system element has a VLSI array with redundant areas and an ABIST (Array Built-In Self Test) system having mirror image fuse registers enabling scan of failed addresses to be used to replace hardware errors detected during power-on at a customer location. The ABIST controller allows self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Test sequence is controlled by logical test vectors, which can be changed, making the task of developing complex testing sequences relatively easy and useful for enabling array self-tests to be performed in a customer's office at power-on reset.Type: GrantFiled: April 3, 1997Date of Patent: September 8, 1998Assignee: International Business Machines CorporationInventors: William Vincent Huott, Tin-Chee Lo, Pradip Patel, Timothy John Slegel
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Patent number: 5661732Abstract: Computer system element has a VLSI array with redundant areas and an ABIST (Array Built-In Self Test system). The ABIST controller allows self test functions (e.g. test patterns, read/write access, and test sequences) to be used with dual logical views to reduce test time. The ABIST generates pseudo-random address patterns for improved test coverage. A jump-to-third pointer control command enables branching to perform looping after a background has been filled. A data register is divided into multiple sections to enable a Walking/Marching pattern to be executed individually and concurrently in the dual views to further reduce test times.Type: GrantFiled: December 14, 1995Date of Patent: August 26, 1997Assignee: International Business Machines CorporationInventors: Tin-Chee Lo, William Vincent Huott
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Patent number: 5659551Abstract: Computer system element has a VLSI array with redundant areas and an ABIST (Array Built-In Self Test) system having mirror image fuse registers enabling scan of failed addresses to be used to replace hardware errors detected during power-on at a customer location. The ABIST controller allows self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Test sequence is controlled by logical test vectors, which can be changed, making the task of developing complex testing sequences relatively easy and useful for enabling array self-tests to be performed in a customer's office at power-on reset.Type: GrantFiled: December 14, 1995Date of Patent: August 19, 1997Assignee: International Business Machines CorporationInventors: William Vincent Huott, Tin-Chee Lo, Pradip Patel, Timothy John Slegel
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Patent number: 5565808Abstract: A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a pulsed output to the output logic circuit. Circuitry is provided to control the self-reset operation of the input logic circuit such that the reset does not occur until a predetermined period of time after the leading edge of the clock pulse latching the state of the input self-reset circuit in the latch. The output of the latch is gated from the latch to the output self-reset circuit under the control of a chopper circuit. The chopper circuit provides a control pulse to gate the state of the latch to the output self-reset circuit a predetermined period of time after the data has been latched. The control pulse has a duration sufficient to assure that the state of the latch is registered in the output self-reset logic.Type: GrantFiled: June 5, 1995Date of Patent: October 15, 1996Assignee: International Business Machines CorporationInventor: Tin-chee Lo
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Patent number: 5543735Abstract: A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a pulsed output to the output logic circuit. Circuitry is provided to control the self-reset operation of the input logic circuit such that the reset does not occur until a predetermined period of time after the leading edge of the clock pulse latching the state of the input self-reset circuit in the latch. The output of the latch is gated from the latch to the output self-reset circuit under the control of a chopper circuit. The chopper circuit provides a control pulse to gate the state of the latch to the output self-reset circuit a predetermined period of time after the data has been latched. The control pulse has a duration sufficient to assure that the state of the latch is registered in the output self-reset logic.Type: GrantFiled: June 2, 1995Date of Patent: August 6, 1996Assignee: International Business Machines CorporationInventor: Tin-chee Lo
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Patent number: 5488319Abstract: A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a pulsed output to the output logic circuit. Circuitry is provided to control the self-reset operation of the input logic circuit such that the reset does not occur until a predetermined period of time after the leading edge of the clock pulse latching the state of the input self-reset circuit in the latch. The output of the latch is gated from the latch to the output self-reset circuit under the control of a chopper circuit. The chopper circuit provides a control pulse to gate the state of the latch to the output self-reset circuit a predetermined period of time after the data has been latched. The control pulse has a duration sufficient to assure that the state of the latch is registered in the output self-reset logic.Type: GrantFiled: August 18, 1994Date of Patent: January 30, 1996Assignee: International Business Machines CorporationInventor: Tin-chee Lo
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Patent number: 5479640Abstract: A memory access system for improving memory access when addressing dynamic random access modules (DRAMs). The memory access system includes a main memory and a memory controller. To improve memory access, both the memory controller and the main memory hardware remember the row address of the last access. Macro operation commands for fetch and store contain the last row address. The main memory hardware redrives that row address to the DRAMs after completion of an access, so that the memory controller need not provide a row address to the memory for each command of a command sequence.Type: GrantFiled: June 30, 1993Date of Patent: December 26, 1995Assignee: International Business Machines CorporationInventors: Frank P. Cartman, Brian W. Curran, Matthew A. Krygowski, Tin-Chee Lo, Sandy N. Luu, Sanjay B. Patel, William W. Shen
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Patent number: 5359722Abstract: A method for reducing fetch time in a computer system provides a memory fetch cycle that is shorter than the memory store cycle. Each chip of the computer system has at least one dynamic random access memory array (DRAM) and a small high speed cache static random access memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and recovery in the DRAM. The RAS starts DRAM recovery for a fetch cycle at or near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that control DRAM recovery while fetching during DRAM data from the SRAMs, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.Type: GrantFiled: July 23, 1990Date of Patent: October 25, 1994Assignee: International Business Machines CorporationInventors: Shiu K. Chan, Joseph H. Datres, Jr., Tin-Chee Lo
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Patent number: 5138705Abstract: A memory structure is described as comprised of a large number of fixed-size page frames. Each page frame in the memory is spread among all chips in the memory. The size of the memory structure may be extended or expanded by adding the same type of high-capacity chip originally used to construct the memory. (The chips may be constructed of semiconductor DRAM technology.) When the memory is extended/expanded, the fixed-size page frames have their lateral dimension decreased and their length increased, in accordance with the increase in the number of chips in the memory. A shift register on each chip accommodates the moving of pages within the memory structure as the page-frame shape and the redistribution of the page frame locations in the memory are changed when the number of chips in the memory structure is changed, without requiring any change in the internal structure of the chips.Type: GrantFiled: June 26, 1989Date of Patent: August 11, 1992Assignee: International Business Machines CorporationInventors: Tin-Chee Lo, Arnold Weinberger
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Patent number: 5058115Abstract: In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, clip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.Type: GrantFiled: March 10, 1989Date of Patent: October 15, 1991Assignee: International Business Machines Corp.Inventors: Robert M. Blake, Douglas C. Bossen, Chin-Long Chen, John A. Fifield, Howard L. Kalter, Tin-Chee Lo