Patents by Inventor Tin-Fook Ngai

Tin-Fook Ngai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10372450
    Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Victor W. Lee, Daehyun Kim, Tin-Fook Ngai, Jayashankar Bharadwaj, Albert Hartono, Sara Baghsorkhi, Nalini Vasudevan
  • Patent number: 10277707
    Abstract: Apparatuses, methods and storage medium associated with a memcached system are disclosed herewith. In embodiments, a client device of the memcached system may include memory and one or more processors coupled with the memory. Further, the client device may include memcached logic configured to receive a request to Get or Set a value corresponding to a key in the memcached system, determine, in response to the receive, whether the key results in a hit in a local cache maintained in memory by the memcached logic, and service the Get or Set request based at least in part on whether a result of the determine indicates the key results in a hit in the local cache. In embodiments, a server of the memcached system may include complement memcached logic to server a Get, Set or an Update request. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Xiangbin Wu, Shunyu Zhu, Yingzhe Shen, Tin-Fook Ngai
  • Publication number: 20180321936
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Application
    Filed: April 2, 2018
    Publication date: November 8, 2018
    Inventors: Edward Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Collins, James Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Publication number: 20180307484
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Application
    Filed: February 20, 2018
    Publication date: October 25, 2018
    Inventors: Ed Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Collins, James Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Publication number: 20180225118
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Inventors: Ed Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Collins, James Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Publication number: 20180225117
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Inventors: Ed Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Collins, James Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Patent number: 9952859
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Ed Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Collins, James Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Publication number: 20180067743
    Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.
    Type: Application
    Filed: July 11, 2017
    Publication date: March 8, 2018
    Applicant: Intel Corporation
    Inventors: Victor W. LEE, Daehyun KIM, Tin-Fook NGAI, Jayashankar BHARADWAJ, Albert HARTONO, Sara BAGHSORKHI, Nalini VASUDEVAN
  • Publication number: 20180060049
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Application
    Filed: June 6, 2017
    Publication date: March 1, 2018
    Inventors: DAVID J. SAGER, RUCHIRA SASANKA, RON GABOR, SHLOMO RAIKIN, JOSEPH NUZMAN, LEEOR PELED, JASON A. DOMER, HO-SEOP KIM, YOUFENG WU, KOICHI YAMADA, TIN-FOOK NGAI, HOWARD H. CHEN, JAYARAM BOBBA, JEFFREY J. COOK, OMAR M. SHAIKH, SURESH SRINIVAS
  • Publication number: 20170255560
    Abstract: A processing device includes a processing core, coupled to a memory, to execute a task including a code segment identified as being monitored and a kernel recorder, coupled to the processing core via a core interface. The kernel recorder includes a first filter circuit to responsive to determining that the task being executed enters the code segment, set the kernel recorder to a first mode under which the kernel recorder is to record, in a first record, a plurality of memory addresses accessed by the code segment, and responsive to determining that the execution of the task exits the code segment, set the kernel recorder to a second mode under which the kernel recorder is to detect a write operation to a memory address recorded in the first record and record the memory address in a second record.
    Type: Application
    Filed: September 25, 2014
    Publication date: September 7, 2017
    Inventors: Sai LUO, Tin-Fook NGAI, Hu CHEN, Xiaocheng ZHOU, Chunxiao LIN, Kang ZHAO
  • Patent number: 9753727
    Abstract: Generally, this disclosure provides technologies for generating and executing partially vectorized code that may include backward dependencies within a loop body of the code to be vectorized. The method may include identifying backward dependencies within a loop body of the code; selecting one or more ranges of iterations within the loop body, wherein the selected ranges exclude the identified backward dependencies; and vectorizing the selected ranges. The system may include a vector processor configured to provide predicated vector instruction execution, loop iteration range enabling, and dynamic loop dependence checking.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: September 5, 2017
    Assignee: INTEL CORPORATION
    Inventors: Tin-Fook Ngai, Chunxiao Lin, Yingzhe Shen, Chao Zhang
  • Patent number: 9703558
    Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Victor W. Lee, Daehyun Kim, Tin-Fook Ngai, Jayashankar Bharadwaj, Albert Hartono, Sara Baghsorkhi, Nalini Vasudevan
  • Patent number: 9672019
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Grant
    Filed: December 25, 2010
    Date of Patent: June 6, 2017
    Assignee: Intel Corporation
    Inventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffery J. Cook, Omar M. Shaikh, Suresh Srinivas
  • Publication number: 20160283438
    Abstract: A processing device includes a first processor module comprising a first core designed according to a first instruction set (ISA), and a second processor module comprising a second core designed according to a second ISA. The first and second processor modules are fabricated on a same die.
    Type: Application
    Filed: December 23, 2013
    Publication date: September 29, 2016
    Inventors: Hu Tiger CHEN, Liang CHEN, Chunxiao LIN, Sai LUO, Hai Ge TIAN, Rui Gang WANG, Tin-Fook NGAI
  • Publication number: 20160285997
    Abstract: Apparatuses, methods and storage medium associated with a memcached system are disclosed herewith. In embodiments, a client device of the memcached system may include memory and one or more processors coupled with the memory. Further, the client device may include memcached logic configured to receive a request to Get or Set a value corresponding to a key in the memcached system, determine, in response to the receive, whether the key results in a hit in a local cache maintained in memory by the memcached logic, and service the Get or Set request based at least in part on whether a result of the determine indicates the key results in a hit in the local cache. In embodiments, a server of the memcached system may include complement memcached logic to server a Get, Set or an Update request. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 26, 2014
    Publication date: September 29, 2016
    Inventors: Xiangbin Wu, Shunyu Zhu, Yingzhe Shen, Tin-Fook Ngai
  • Patent number: 9442721
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: September 13, 2016
    Assignee: Intel Corporation
    Inventors: Edward T. Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Colins, James P. Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Publication number: 20160216971
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Application
    Filed: March 31, 2016
    Publication date: July 28, 2016
    Inventors: Ed Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Collins, James Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Patent number: 9301198
    Abstract: Embodiments of an enhanced Node B (eNB) configured for use in a cooperative radio access networks (C-RAN) and method for central baseband unit (BBU) processing are generally described herein. In some embodiments, the eNB may include a baseband unit (BBU) processing pool comprising a plurality of processing units. The BBU processing pool is configured to share the processing load of several sectors. A control unit may monitor the processing load of the processing units and perform dynamic load sharing by migrating the baseband processing between the processing units without changing a carrier used by user equipment operating with a sector.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: March 29, 2016
    Assignee: Intel Corporation
    Inventors: Guangjie Li, Xuebin Yang, Senjie Zhang, Tin-Fook Ngai
  • Patent number: 9268626
    Abstract: An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: February 23, 2016
    Assignee: INTEL CORPORATION
    Inventors: Jayashankar Bharadwaj, Victor W. Lee, Kim Daehyun, Nalini Vasudevan, Tin-Fook Ngai, Albert Hartono, Sara S. Baghsorkhi
  • Patent number: 9189230
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: November 17, 2015
    Assignee: Intel Corporation
    Inventors: Edward T. Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Collins, James P. Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai