Abstract: A multiplier circuit multiplies a reference voltage to increase the level of the reference voltage. A feedback circuit of the multiplier circuit stabilize the multiplier circuit such that a feedback voltage of said feedback circuit tends to equalize the reference voltage. The feedback circuit is free from capacitance which would unstabilize the feedback circuit. A voltage divider outside of the feedback circuit reduces the multiplied voltage of the multiplier circuit.

Abstract: A voltage reference circuit includes: an amplifier A1 with low open loop output impedance, an output of the amplifier is coupled to a first input of the amplifier A1; and a first resistor R1 coupled between the output of the amplifier A1 and a reference node 30, the first resistor R1 has a resistance substantially equally to the low open loop output impedance, whereby a low frequency impedance at the reference node 30 is substantially equal to the resistance.

Abstract: A digital-to-analog converter includes a first array of resistors 10-16 connected in series; a switch matrix 20 coupled to the first array of resistors 10-16; a first variable resistor RTOP coupled to a first end of the first array of resistors 10-16; and a second variable resistor RBOT coupled to a second end of the first array of resistors 10-16, the first variable resistor RTOP and the second variable resistor RBOT having a combined resistance that is a fixed resistance value.

Abstract: The current-integrating analog-to-digital converter includes a first charge storage device C.sub.1 ; a second charge storage device C.sub.2 ; an input current I.sub.in coupled to the first charge storage device C.sub.1 for a first time period; a variable reference current I.sub.dac coupled to the second charge storage device C.sub.2 for a second time period; and a comparator 20 for comparing the voltage on the first charge storage device C.sub.1 with the voltage on the second charge storage device C.sub.2.

Abstract: A System and method for calibrating a chip after packaging including providing a packaged chip, providing programmable non-volatile storage having a plurality of non-volatile storage elements in the chip and providing a volatile storage having a plurality of volatile storage elements in the chip with one volatile storage element associated with one non-volatile storage element. The chip includes circuitry responsive to a predetermined signal to permit the non-volatile storage to be programmed in accordance with data stored in the volatile storage and to a predetermined signal to prevent external alteration of the non-volatile storage. The non-volatile storage is preferably a plurality of fuses. The volatile storage is preferably a shift register.