Patents by Inventor Tin Poay Chuah
Tin Poay Chuah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190342996Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.Type: ApplicationFiled: July 16, 2019Publication date: November 7, 2019Applicant: Intel CorporationInventors: Chee Ling Wong, Wil Choon Song, Khang Choong Yong, Eng Huat Goh, Mohd Muhaiyiddin Bin Abdullah, Tin Poay Chuah
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Publication number: 20190279949Abstract: A capacitor loop substrate assembly may include a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects may be formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.Type: ApplicationFiled: November 20, 2017Publication date: September 12, 2019Inventors: Jenny Shio Yin ONG, Tin Poay CHUAH, Chin Lee KUAN
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Publication number: 20190261504Abstract: A folded circuit board includes a first circuit board and a second circuit board. The first circuit board and second circuit board are coupled together through a flexible interconnect. One or more folding guides are coupled to one of the first circuit board or second circuit board. The one or more folding guides extend beyond a first edge of the one of the first circuit board or second circuit board. The one or more folding guides include a curved sidewall configured to guide the flexible interconnect when the first circuit board is folded over the second circuit board. In one embodiment, the one or more folding guides are grounded to reduce EMI emissions.Type: ApplicationFiled: April 30, 2019Publication date: August 22, 2019Inventors: Tin Poay Chuah, Yew San Lim, Boon Ping Koh, Phaik Kiau Tan
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Patent number: 10355384Abstract: In one example an electronic device comprises a chassis and a printed circuit board coupled to the chassis and comprising a body formed from a plurality of laminate layers, and at least one receptacle formed in the body and comprising at least one data connector positioned in the receptacle to provide a communication connection. Other examples may be described.Type: GrantFiled: September 23, 2015Date of Patent: July 16, 2019Assignee: INTEL CORPORATIONInventors: Kit Chew Chee, Ahmad Jalaluddin Yusof, Tin Poay Chuah
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Patent number: 10356902Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.Type: GrantFiled: December 26, 2015Date of Patent: July 16, 2019Assignee: Intel CorporationInventors: Chee Ling Wong, Wil Choon Song, Khang Choong Yong, Eng Huat Goh, Mohd Muhaiyiddin Bin Abdullah, Tin Poay Chuah
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Publication number: 20190208643Abstract: A printed circuit board (PCB) comprises a blind via and a discrete component vertically embedded within the blind via.Type: ApplicationFiled: September 30, 2016Publication date: July 4, 2019Inventors: Tin Poay CHUAH, Min Suet LIM, Hoay Tien TEOH, Mooi Ling CHANG, Chin Lee KUAN
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Patent number: 10297541Abstract: Microelectronic devices having a multiple-component substrate assembly. A primary supports one or more integrated circuits, and an auxiliary substrate is coupled to, and makes electrical connections with, the primary substrate. The primary substrate will define a pinout for some or all contacts of the integrated circuit, and the auxiliary substrate will provide an additional pinout option. Different configurations of a single primary substrate may be adapted to different applications through use of different configurations of auxiliary substrates.Type: GrantFiled: November 18, 2016Date of Patent: May 21, 2019Assignee: Intel CorporationInventors: Min Suet Lim, Mooi Ling Chang, Eng Huat Goh, Say Thong Tony Tan, Tin Poay Chuah
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Publication number: 20190131227Abstract: Techniques and mechanisms to facilitate connectivity between circuit components via a substrate. In an embodiment, a microelectronic device includes a substrate, wherein a recess region extends from the first side of the substrate and only partially toward a second side of the substrate. First input/output (IO) contacts of a first hardware interface are disposed in the recess region. The first IO contacts are variously coupled to each to a respective metallization layer of the substrate, wherein the recess region extends though one or more other metallization layers of the substrate. In another embodiment, the microelectronic device further comprises second IO contacts of a second hardware interface, the second IO contacts to couple the microelectronic device to a printed circuit board.Type: ApplicationFiled: July 1, 2016Publication date: May 2, 2019Inventors: Howe Yin LOO, Sujit SHARAN, Tin Poay CHUAH, Ananth PRABHAKUMAR
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Patent number: 10211069Abstract: An apparatus including a printed circuit board including a body of a plurality of alternating layers of conductive material and insulating material; and a package including a die disposed within the body of the printed circuit board. A method including forming a printed circuit board including a core and a build-up section including alternating layers of conductive material and insulating material coupled to the core; and coupling a package including a die to the core of the printed circuit board such that at least a portion of a sidewall of the package is embedded in at least a portion of the build-up section. An apparatus including a printed circuit board including a body; a computing device including a package including a microprocessor disposed within the body of the printed circuit board; and a peripheral device that provides input or output to the computing device.Type: GrantFiled: October 30, 2015Date of Patent: February 19, 2019Assignee: Intel CorporationInventor: Tin Poay Chuah
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Publication number: 20190045621Abstract: In embodiments, a device may include a single electromagnetic interference (EMI) shield plate that defines an enclosed area. The EMI shield plate may have an inner surface and an outer surface opposite the inner surface. The device may further include a first printed circuit board (PCB) coupled with the inner surface, wherein the first PCB is within the enclosed area. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 25, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Tin Poay Chuah, Yew San Lim, Khai Ern Ke See, Khang Choong Yong, Kevin J. Byrd
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Publication number: 20190008052Abstract: Disclosed herein is a multi-planar circuit board, as well as related structures and methods. In an embodiment, a circuit board may include a first surface, a first section having the first surface in a first plane, a second section having the first surface in a second plane, and a third section connecting the first and second sections, where the third section defines a gradient between the first and second planes, and where all sections are sections within a contiguous board. In another embodiment, circuit board may further include a first component having a first thickness coupled on the first face of the first section, and a second component having a second thickness, greater than the first component, coupled on the first face of the second section, where the second section is in a lower plane, and where the overall thickness is the circuit board thickness plus the second thickness.Type: ApplicationFiled: June 8, 2018Publication date: January 3, 2019Applicant: Intel CorporationInventors: Eng Huat Goh, Min Suet Lim, Tin Poay Chuah, Han Kung Chua
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Publication number: 20190006356Abstract: An apparatus is provided which comprises: one or more dielectric layers forming a substrate, one or more first conductive contacts on a top surface of the substrate, one or more second conductive contacts on a bottom surface of the substrate opposite of the top surface, and one or more discrete capacitors conductively coupled with one or more of the first and second conductive contacts, the one or more discrete capacitors embedded within the substrate between the top surface and the bottom surface. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: May 24, 2018Publication date: January 3, 2019Applicant: Intel CorporationInventors: Seok Ling Lim, Jenny Shio Yin Ong, Tin Poay Chuah, Hon Wah Chew
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Publication number: 20180233841Abstract: In one example an electronic device comprises a chassis and a printed circuit board coupled to the chassis and comprising a body formed from a plurality of laminate layers, and at least one receptacle formed in the body and comprising at least one data connector positioned in the receptacle to provide a communication connection. Other examples may be described.Type: ApplicationFiled: September 23, 2015Publication date: August 16, 2018Applicant: Intel CorporationInventors: Kit Chew Chee, Ahmad Jalaluddin Yusof, Tin Poay Chuah
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Publication number: 20180145016Abstract: Microelectronic devices having a multiple-component substrate assembly. A primary supports one or more integrated circuits, and an auxiliary substrate is coupled to, and makes electrical connections with, the primary substrate. The primary substrate will define a pinout for some or all contacts of the integrated circuit, and the auxiliary substrate will provide an additional pinout option. Different configurations of a single primary substrate may be adapted to different applications through use of different configurations of auxiliary substrates.Type: ApplicationFiled: November 18, 2016Publication date: May 24, 2018Inventors: Min Suet Lim, Mooi Ling Chang, Eng Huat Goh, Say Thong Tony Tan, Tin Poay Chuah
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Publication number: 20170290154Abstract: Three-dimensional (3-D) volumetric board architectural design provides technical solutions to technical problems facing miniaturization of circuit boards. The 3-D volumetric architecture includes using more of the unused volume in the vertical dimension (e.g., Z-dimension) to increase the utilization of the total circuit board volume. The 3-D volumetric architecture is realized by mounting components on a first PCB and on a second PCB, and inverting and suspending the second PCB above the first PCB. The use of 3-D volumetric board architectural design further enables formation of a shielded FEMIE, providing shielding and improved volumetric use with little or no reduction in system performance or increase in system Z-height.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Khang Choong Yong, Stephen H. Hall, Tin Poay Chuah, Boon Ping Koh, Eng Huat Goh
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Publication number: 20170188461Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.Type: ApplicationFiled: December 26, 2015Publication date: June 29, 2017Inventors: Chee Ling Wong, Wil Choon Song, Khang Choong Yong, Eng Huat Goh, Mohd Muhaiyiddin Bin Abdullah, Tin Poay Chuah
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Publication number: 20170086298Abstract: Techniques and mechanisms to provide interconnect structures of a substrate such as a printed circuit board. In an embodiment, a first side of a substrate has disposed thereon a hardware interface contacts to couple the substrate to a packaged IC device. The contacts define a footprint area, where an overlap region of the substrate is defined by a projection of the footprint area from the first side to a second side of the substrate. The substrate forms a recess extending from one of the first side and the second side. In another embodiment, at least part of the recess is within the overlap region, and interconnect structures of the substrate facilitate connection between the packaged IC device and a capacitor disposed at least partially in the recess. Positioning of the capacitor within the overlap region enables improvements in substrate space efficiency, power delivery and/or signal noise.Type: ApplicationFiled: September 23, 2015Publication date: March 23, 2017Inventors: Tin Poay Chuah, Min Suet Lim, Ping Ping Ooi, Eng Huat Goh, See Chin Chow
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Publication number: 20160049316Abstract: An apparatus including a printed circuit board including a body of a plurality of alternating layers of conductive material and insulating material; and a package including a die disposed within the body of the printed circuit board. A method including forming a printed circuit board including a core and a build-up section including alternating layers of conductive material and insulating material coupled to the core; and coupling a package including a die to the core of the printed circuit board such that at least a portion of a sidewall of the package is embedded in at least a portion of the build-up section. An apparatus including a printed circuit board including a body; a computing device including a package including a microprocessor disposed within the body of the printed circuit board; and a peripheral device that provides input or output to the computing device.Type: ApplicationFiled: October 30, 2015Publication date: February 18, 2016Inventor: Tin Poay Chuah
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Patent number: 9202782Abstract: An apparatus including a printed circuit board including a body of a plurality of alternating layers of conductive material and insulating material; and a package including a die disposed within the body of the printed circuit board. A method including forming a printed circuit board including a core and a build-up section including alternating layers of conductive material and insulating material coupled to the core; and coupling a package including a die to the core of the printed circuit board such that at least a portion of a sidewall of the package is embedded in at least a portion of the build-up section. An apparatus including a printed circuit board including a body; a computing device including a package including a microprocessor disposed within the body of the printed circuit board; and a peripheral device that provides input or output to the computing device.Type: GrantFiled: January 7, 2013Date of Patent: December 1, 2015Assignee: Intel CorporationInventor: Tin Poay Chuah
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Publication number: 20140191420Abstract: An apparatus including a printed circuit board including a body of a plurality of alternating layers of conductive material and insulating material; and a package including a die disposed within the body of the printed circuit board. A method including forming a printed circuit board including a core and a build-up section including alternating layers of conductive material and insulating material coupled to the core; and coupling a package including a die to the core of the printed circuit board such that at least a portion of a sidewall of the package is embedded in at least a portion of the build-up section. An apparatus including a printed circuit board including a body; a computing device including a package including a microprocessor disposed within the body of the printed circuit board; and a peripheral device that provides input or output to the computing device.Type: ApplicationFiled: January 7, 2013Publication date: July 10, 2014Inventor: Tin Poay Chuah