Patents by Inventor Ting-An Chien

Ting-An Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210143324
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, part of the MTJ stack is removed, a first cap layer is formed on a sidewall of the MTJ stack, and the first cap layer and the MTJ stack are removed to form a first MTJ and a second MTJ.
    Type: Application
    Filed: December 9, 2019
    Publication date: May 13, 2021
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Shih-Wei Su, Ting-An Chien
  • Publication number: 20210119110
    Abstract: A cell structure of magnetoresistive RAM includes a synthetic anti-ferromagnetic (SAF) layer to serve as a pinned layer; a barrier layer, disposed on the SAF layer; and a magnetic free layer, disposed on the barrier layer. The SAF layer includes: a first magnetic layer; a second magnetic layer; and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first magnetic layer and the second magnetic layer interfacing with the spacer layer.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Ting-An Chien
  • Publication number: 20210098599
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Wei-Ting Chien, Liang-Yin Chen, Yi-Hsiu Liu, Tsung-Lin Lee, Huicheng Chang
  • Publication number: 20210087912
    Abstract: A slurry analysis system (14) for estimating a first characteristic of a slurry (12) having a plurality of particles (18) suspended in a dispersion medium (20) can include a flow restriction assembly (40); a sensor assembly (43) that senses a sensed condition of the slurry (12) as it flows through the flow restriction assembly (40); and a control and analysis system (26) that estimates the first characteristic of the slurry (12) based on the sensed condition. Further, the control and analysis system (26) can select a selected clogging behavior using the sensed condition, and estimate the first characteristic based on the selected clogging behavior.
    Type: Application
    Filed: September 24, 2020
    Publication date: March 25, 2021
    Inventors: Takashi Nagata, Ting-Chien Teng, Kiyoshi Nozaki, Yohei Konishi
  • Publication number: 20210074917
    Abstract: A method of forming a resistive random access memory cell includes the following steps. A first electrode layer, a blanket resistive switching material layer and a second electrode layer are formed on a layer sequentially. The second electrode layer is patterned to form a second electrode. The blanket resistive switching material layer is patterned to form a resistive switching material layer. An oxygen implanting process is performed to implant oxygen in two sidewall parts of the resistive switching material layer.
    Type: Application
    Filed: October 1, 2019
    Publication date: March 11, 2021
    Inventors: Shih-Wei Su, Da-Jun Lin, Bin-Siang Tsai, Ya-Jyuan Hung, Ting-An Chien
  • Patent number: 10937523
    Abstract: Methods, systems and computer-readable storage media relate to generating one or more consensus sequences. The methods may include determining a group of one or more reads with each main position without diversity from a group of one or more aligned reads based on diversity status of each main position, each group including sequence data disposed at a plurality of main positions and a plurality of secondary position regions disposed adjacent to the main positions. The methods may also include determining legitimate sequence data from each second position region having one or more nucleotides for each group of one or more reads without diversity; and generating a consensus sequence including sequence data disposed at each main position without diversity and legitimate sequence data disposed at each secondary position region for each group of one or more reads with each main position without diversity.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: March 2, 2021
    Assignee: Emory University
    Inventors: Dario A. Dilernia, Jung-Ting Chien, Eric Hunter
  • Publication number: 20210048859
    Abstract: A circuit includes: a first interface circuit supporting multiple first interface operating modes respectively corresponding to different versions of a first data transmission protocol; a second interface circuit supporting multiple second interface operating modes respectively corresponding to different versions of a second data transmission protocol; a control circuit configured to operably instruct the first interface circuit to operate in a first target operating mode selected from the multiple first interface operating modes, and configured to operably instruct the second interface circuit to operate in a second target operating mode selected from the multiple second interface operating modes; wherein a difference between a nominal data rate of the first target operating mode and a nominal data rate of the second target operating mode is less than a predetermined threshold.
    Type: Application
    Filed: July 15, 2020
    Publication date: February 18, 2021
    Inventors: Yi Ting CHIEN, Cheng Yuan HSIAO, Chih Yu HSU, Sung Kao LIU, Wei Hung CHUANG
  • Publication number: 20210050511
    Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a magnetic tunneling junction (MTJ) on the metal interconnection; forming a top electrode on the MTJ; and forming a trapping layer on the top electrode for trapping hydrogen. Preferably, the trapping layer includes a concentration gradient, in which a concentration of hydrogen decreases from a top surface of the top electrode toward the MTJ.
    Type: Application
    Filed: September 8, 2019
    Publication date: February 18, 2021
    Inventors: Da-Jun Lin, Tai-Cheng Hou, Bin-Siang Tsai, Ting-An Chien
  • Patent number: 10892348
    Abstract: A method of rounding fin-shaped structures includes the following steps. A substrate including fin-shaped structures, and pad oxide caps and pad nitride caps covering the fin-shaped structures from bottom to top are provided. An isolation structure fills between the fin-shaped structures. A removing process is performed to remove a top part of the isolation structure and expose top parts of the fin-shaped structures. An oxidation process is performed to oxidize sidewalls of the top parts of the fin-shaped structures, thereby forming oxidized parts covering sidewalls of the top parts of the fin-shaped structures. The pad nitride caps are removed. The pad oxide caps and the oxidized parts are removed at the same time, thereby forming rounding fin-shaped structures.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao-Hsuan Chang, Bin-Siang Tsai, Ting-An Chien, Yi-Liang Ye
  • Publication number: 20200411384
    Abstract: A method for forming a semiconductor device is provided. A dielectric layer is formed on a substrate. First and second gate trenches are formed in the dielectric layer. First and second spacers are disposed in the first and the second gate trenches, respectively. A patterned photoresist is formed on the dielectric layer. The patterned photoresist masks the first region and exposes the second region. Multiple cycles of spacer trimming process are performed to trim a sidewall profile of the second spacer. Each cycle comprises a step of oxygen stripping and a successive step of chemical oxide removal. The patterned photoresist is then removed to reveal the first region.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Yao-Hsien Chung, Hao-Hsuan Chang, Ting-An Chien, Bin-Siang Tsai
  • Publication number: 20200411672
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Application
    Filed: September 6, 2020
    Publication date: December 31, 2020
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li, Tien-Shun Chang
  • Publication number: 20200411681
    Abstract: A method for forming a semiconductor device is disclosed. A substrate having at least two fins thereon and an isolation trench between the at least two fins is provided. A liner layer is then deposited on the substrate. The liner layer conformally covers the two fins and interior surface of the isolation trench. A stress-buffer film is then deposited on the liner layer. The stress-buffer film completely fills a lower portion that is located at least below half of a trench depth of the isolation trench. A trench-fill oxide layer is then deposited to completely fill an upper portion of the isolation trench.
    Type: Application
    Filed: June 25, 2019
    Publication date: December 31, 2020
    Inventors: Shih-Wei Su, Hao-Hsuan Chang, Chih-Wei Chang, Chi-Hsuan Cheng, Ting-An Chien, Bin-Siang Tsai
  • Publication number: 20200395413
    Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part . The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.
    Type: Application
    Filed: July 17, 2019
    Publication date: December 17, 2020
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Ya-Jyuan Hung, Chin-Chia Yang, Ting-An Chien
  • Patent number: 10868142
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ting Chien, Liang-Yin Chen, Yi-Hsiu Liu, Tsung-Lin Lee, Huicheng Chang
  • Patent number: 10859841
    Abstract: An augmented reality image device is provided and includes a display, a mirror, a reflector, and a front mask. The display has a first side and a second side opposite to the first side. The mirror and the front mask are disposed at the first side of the display. The first reflector is disposed at the second side of the display. The front mask has a reflection area. The display emits an image light from the first side to the mirror. The image light is reflected by the mirror to the reflector. The reflector reflects the image light to the reflection area of the front mask. Therefore, a virtual image caused by the image light in the reflection area is combined with a real image to generate an augmented reality image.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 8, 2020
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Jui-Ting Chien, Sheng-Hsiu Tseng
  • Publication number: 20200379833
    Abstract: An error handling method for a transmission interface connecting between a first device and a second device for performing data transmission between the first device and the second device, wherein a connection type between the transmission interface and the first device is a direct interface (DI) and the connection type between the transmission interface and the second device is an indirect interface (II), and the error handling method comprises: when an error is detected at the direct interface, reporting an error event to a host of the first device; when an error is detected at the indirect interface, attempting to handle the error without letting the host discover it; and when the error detected at the indirect interface is determined as unable to be solved, reporting another error event to the host.
    Type: Application
    Filed: December 12, 2019
    Publication date: December 3, 2020
    Inventors: Cheng-Yuan Hsiao, Sung-Kao Liu, Yi-Ting Chien, Wei-Hung Chuang, Chih-Yu Hsu
  • Publication number: 20200350199
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a pad layer adjacent to two sides of trench; forming a dielectric layer to fill the trench; and performing a dry etching process to remove the pad layer and part of the dielectric layer to form a shallow trench isolation (STI). Preferably, the dry etching process comprises a non-plasma etching process.
    Type: Application
    Filed: June 4, 2019
    Publication date: November 5, 2020
    Inventors: Hao-Hsuan Chang, Hung-Chun Lee, Shu-Ming Yeh, Ting-An Chien, Bin-Siang Tsai
  • Publication number: 20200343371
    Abstract: A method of rounding fin-shaped structures includes the following steps. A substrate including fin-shaped structures, and pad oxide caps and pad nitride caps covering the fin-shaped structures from bottom to top are provided. An isolation structure fills between the fin-shaped structures. A removing process is performed to remove a top part of the isolation structure and expose top parts of the fin-shaped structures. An oxidation process is performed to oxidize sidewalls of the top parts of the fin-shaped structures, thereby forming oxidized parts covering sidewalls of the top parts of the fin-shaped structures. The pad nitride caps are removed. The pad oxide caps and the oxidized parts are removed at the same time, thereby forming rounding fin-shaped structures.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Inventors: Hao-Hsuan Chang, Bin-Siang Tsai, Ting-An Chien, Yi-Liang Ye
  • Patent number: 10770570
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li, Tien-Shun Chang
  • Publication number: 20200259001
    Abstract: In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant decreasing in a direction extending from a top of the fin to a bottom of the fin.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Inventors: Chia-Ling Chan, Liang-Yin Chen, Wei-Ting Chien