Patents by Inventor Ting-An Chien
Ting-An Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240106287Abstract: A rotor structure includes a laminated silicon steel sheet structure, end plates, a shaft and a thermoset plastic key. Each silicon steel sheet includes a shaft hole and at least one sheet matching portion, and the sheet matching portion is connected to the shaft hole. The shaft passes through the shaft holes of the silicon steel sheets and the at least one shaft matching portions aligned with the at least one sheet matching portion to form an axial-direction injection passageway. The end plate includes an injection port connected to the axial-direction injection passageway. The thermoset plastic key is formed in the axial-direction injection passageway formed of the aligned shaft matching portions and sheet matching portion by transfer injection molding. The injection material is filled in magnet slots for securing magnets. A rotor manufacturing process is also provided.Type: ApplicationFiled: June 14, 2023Publication date: March 28, 2024Inventors: Chia-Yen CHIEN, Tzu-Ting HSU
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Patent number: 11921025Abstract: A slurry analysis system (14) for estimating a first characteristic of a slurry (12) having a plurality of particles (18) suspended in a dispersion medium (20) can include a slurry filter (40) that filters the slurry (12); and a control system (26) that estimates the first characteristic of the slurry (12) using a flow rate of a filtrate (50) through the slurry filter (40) and a slurry filtration pressure of the slurry (12).Type: GrantFiled: June 25, 2020Date of Patent: March 5, 2024Assignee: Nikon CorporationInventors: Takashi Nagata, Ting-Chien Teng, Yohei Konishi, Kiyoshi Nozaki
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Publication number: 20240072115Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.Type: ApplicationFiled: February 13, 2023Publication date: February 29, 2024Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
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Patent number: 11915942Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.Type: GrantFiled: June 30, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20240047553Abstract: A method of forming a semiconductor device includes: forming semiconductor fin structures over a substrate, where each of the semiconductor fin structures includes a layer stack over a semiconductor fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material; forming a capping layer over sidewalls and upper surfaces of the semiconductor fin structures; and forming hybrid fins over isolation regions on opposing sides of the semiconductor fin structures, where forming the hybrid fins includes: forming dielectric fins over the isolation regions; and forming dielectric structures over the dielectric fins, which includes: forming an etch stop layer (ESL) over the dielectric fins; doping the ESL with a dopant; and forming a first dielectric material over the doped ESL.Type: ApplicationFiled: January 5, 2023Publication date: February 8, 2024Inventors: Wei-Ting Chien, Liang-Yin Chen, Yee-Chia Yeo
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Publication number: 20240047209Abstract: A method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer, wherein the photoresist layer has an opening, and the opening of the photoresist layer at least has a first sidewall, a second sidewall non-parallel with the first sidewall, and a first corner connecting the first and second sidewalls; performing a first directional ion bombardment process to the first corner of the photoresist layer along a first direction, wherein the first direction is non-perpendicular to both the first and second sidewalls of the photoresist when viewed from top; and after the first directional ion bombardment process is complete, patterning the target layer using the photoresist layer as a patterning mask.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Tien SHEN, Chih-Kai YANG, Hsiang-Ming CHANG, Chun-Yen CHANG, Ya-Hui CHANG, Wei-Ting CHIEN, Chia-Cheng CHEN, Liang-Yin CHEN
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Publication number: 20240032433Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a top electrode on the MTJ, a trapping layer in the top electrode for trapping hydrogen, a first inter-metal dielectric (IMD) layer on the MTJ, and a first metal interconnection in the first IMD layer and on the top electrode. Preferably, a top surface of the trapping layer is lower than a bottom surface of the first IMD layer.Type: ApplicationFiled: October 4, 2023Publication date: January 25, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Tai-Cheng Hou, Bin-Siang Tsai, Ting-An Chien
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Publication number: 20230413690Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.Type: ApplicationFiled: September 6, 2023Publication date: December 21, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shih-Wei Su, Da-Jun Lin, Chih-Wei Chang, Bin-Siang Tsai, Ting-An Chien
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Patent number: 11849649Abstract: A method for fabricating memory cell of magnetoresistive RAM includes forming a memory stack structure on a first electrode layer. The memory stack structure includes a SAF layer to serve as a pinned layer; a magnetic free layer and a barrier layer sandwiched between the SAF layer and the magnetic free layer. A second electrode layer is then formed on the memory stack structure. The SAF layer includes a first magnetic layer, a second magnetic layer, and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first and second magnetic layers, and the second metal element of the first magnetic layer and the second magnetic layer interfaces with the spacer layer.Type: GrantFiled: January 12, 2022Date of Patent: December 19, 2023Assignee: United Microelectronics Corp.Inventors: Da-Jun Lin, Bin-Siang Tsai, Ting-An Chien
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Publication number: 20230386834Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Chih-Kai YANG, Yu-Tien SHEN, Hsiang-Ming CHANG, Chun-Yen CHANG, Ya-Hui CHANG, Wei-Ting CHIEN, Chia-Cheng CHEN, Liang-Yin CHEN
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Patent number: 11818960Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a top electrode on the MTJ, a trapping layer in the top electrode for trapping hydrogen, a first inter-metal dielectric (IMD) layer on the MTJ, and a first metal interconnection in the first IMD layer and on the top electrode. Preferably, a top surface of the trapping layer is lower than a bottom surface of the first IMD layer.Type: GrantFiled: August 5, 2021Date of Patent: November 14, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Tai-Cheng Hou, Bin-Siang Tsai, Ting-An Chien
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Publication number: 20230335401Abstract: A method is disclosed that includes performing a directional ion implantation process on a developed resist pattern to reduce roughness. A substrate can be tilted at a tilt angle with respect to the direction of an incoming ion beam. Ions can be directionally implanted at the tilt angle, along sidewall surfaces of the developed resist pattern to trim roughness from the sidewall surfaces. After implanting, the substrate can be rotated along the axis normal to a surface, and ions can then be directionally implanted at the tilt angle along the sidewall surfaces to further trim roughness from the sidewall surfaces of the developed resist pattern. The directional ion implantation process can be performed over a number of iterations, and during each iteration of the directional ion implantation process, the tilt angle can be adjusted so that the tilt angle is different than during previous iterations.Type: ApplicationFiled: April 14, 2022Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Liang Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11793091Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.Type: GrantFiled: December 7, 2020Date of Patent: October 17, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Wei Su, Da-Jun Lin, Chih-Wei Chang, Bin-Siang Tsai, Ting-An Chien
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Publication number: 20230307525Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.Type: ApplicationFiled: May 31, 2023Publication date: September 28, 2023Inventors: Wei-Ting Chien, Liang-Yin Chen, Yi-Hsiu Liu, Tsung-Lin Lee, Huicheng Chang
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Patent number: 11762293Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.Type: GrantFiled: May 11, 2021Date of Patent: September 19, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hao-Hsuan Chang, Da-Jun Lin, Yao-Hsien Chung, Ting-An Chien, Bin-Siang Tsai, Chih-Wei Chang, Shih-Wei Su, Hsu Ting, Sung-Yuan Tsai
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Patent number: 11753914Abstract: A slurry analysis system (14) for estimating a first characteristic of a slurry (12) having a plurality of particles (18) suspended in a dispersion medium (20) can include a flow restriction assembly (40); a sensor assembly (43) that senses a sensed condition of the slurry (12) as it flows through the flow restriction assembly (40); and a control and analysis system (26) that estimates the first characteristic of the slurry (12) based on the sensed condition. Further, the control and analysis system (26) can select a selected clogging behavior using the sensed condition, and estimate the first characteristic based on the selected clogging behavior.Type: GrantFiled: September 24, 2020Date of Patent: September 12, 2023Inventors: Takashi Nagata, Ting-Chien Teng, Kiyoshi Nozaki, Yohei Konishi
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Publication number: 20230282740Abstract: A high electron mobility transistor including a substrate; a channel layer on the substrate; an electron supply layer on the channel layer; a dielectric passivation layer on the electron supply layer; a gate recess in the dielectric passivation layer and the electron supply layer; a surface modification layer on an interior surface of the gate recess; and a P-type GaN layer in the gate recess and on the surface modification layer. The surface modification layer has a gradient silicon concentration.Type: ApplicationFiled: May 9, 2023Publication date: September 7, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Chang, Yao-Hsien Chung, Shih-Wei Su, Hao-Hsuan Chang, Ting-An Chien, Bin-Siang Tsai
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Publication number: 20230282706Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.Type: ApplicationFiled: May 15, 2023Publication date: September 7, 2023Inventors: Wei-Ting Chien, Wen-Yen Chen, Li-Ting Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang
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Publication number: 20230268442Abstract: In accordance with some embodiments, a source/drain contact is formed by exposing a source/drain region through a first dielectric layer and a second dielectric layer. The second dielectric layer is recessed under the first dielectric layer, and a silicide region is formed on the source/drain region, wherein the silicide region has an expanded width.Type: ApplicationFiled: April 18, 2023Publication date: August 24, 2023Inventors: Wei-Ting Chien, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11723287Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.Type: GrantFiled: September 29, 2022Date of Patent: August 8, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Shih-Wei Su, Bin-Siang Tsai, Ting-An Chien