Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.

Abstract: A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.

Abstract: In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

Abstract: In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

Abstract: Provided are a method and apparatus for transmission processing and a computer-readable storage medium. The method includes determining for at least two transmissions that the starting position of a first transmission is earlier than a point G; and transmitting the first transmission from the starting position of the first transmission to the point G, or transmitting the first transmission from the starting position of the first transmission to the ending position of the first transmission. The point G is a time point of first preset time before the starting position of a second transmission.

Abstract: Disclosed by the embodiments of the present application are a method and an apparatus for determining a HARQ-ACK codebook and HARQ-ACK information. The method for determining an HARQ-ACK codebook includes: setting a plurality of physical downlink shared channel (PDSCH) candidate resources having an overlapped time domain in a downlink slot into one candidate resource group, and determining HARQ-ACK information corresponding to the candidate resource group; and determining a corresponding downlink subslot for the HARQ-ACK information according to a preset rule, and determining a semi-static HARQ-ACK codebook. By means of the present application, the problem that a semi-static HARQ-ACK codebook cannot be determined when a PDSCH candidate resource is cross-subslot can be solved, thereby yielding the effect of meeting the HARQ-ACK requirement in the case that the PDSCH candidate resource is cross-subslot.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.

Abstract: Provided are a response receiving and sending method, a retransmission method, a communication device, and a storage medium. The method includes: sending a transport block to a first communication device through a pre-configured period resource, and receiving a correct response corresponding to the transport block on a pre-configured correct response resource.

Abstract: In one aspect a wireless communications method includes sending, from a first radio terminal to a second radio terminal, a grant message to allow transmission in a future time slot, wherein the future timeslot corresponds to resources of a dummy shared channel in a first direction, and scheduling one or more resources of a shared channel in a second direction with corresponding acknowledgement that overlaps in time with the dummy shared channel in the first direction. In another aspect, a method includes receiving, at a second radio terminal from a first radio terminal, a grant message to allow transmission in a future time slot, wherein the future timeslot corresponds to resources of a dummy shared channel in a first direction, and receiving one or more resources of a shared channel in a second direction with corresponding acknowledgement that overlaps in time with the dummy shared channel in the first direction.

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

Abstract: Provided are a channel configuration method and terminal, a storage medium and an electronic device. The method includes: determining that multiple physical channels overlap in a time domain; and selecting a designated channel to carry information or data in the multiple physical channels.

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack.

Abstract: A motion information candidate list construction method includes: performing a first processing process on all neighboring image blocks of a current image block until a quantity of candidate motion information sets in a candidate motion information list is equal to a first preset value or all the neighboring image blocks are traversed; then traversing at least two extra to be selected motion information sets, and storing, in the candidate motion information list, an extra to be selected motion information set that satisfies a preset condition, until the quantity of candidate motion information sets in the candidate motion information list is equal to a preset quantity value or the extra to be selected motion information sets are traversedextra to be selected motion.

Abstract: This application provides an inter prediction method and apparatus, a video encoder, and a video decoder. The method includes: determining N target picture blocks from M picture blocks in which M neighboring locations of a current picture block are respectively located, where any two of the N target picture blocks are different, M and N are both positive integers, and M is greater than or equal to N; determining candidate motion information of the current picture block based on motion information of the N target picture blocks, and adding the candidate motion information of the current picture block to a motion information candidate list of the current picture block; and performing inter prediction on the current picture block based on the motion information candidate list. In this application, comparison operations during obtaining of the motion information candidate list can be reduced, to improve inter prediction efficiency.

Abstract: Technologies for inter prediction for a block in a video are provided. In one example, a method includes: parsing a bitstream to obtain a syntax element, where the syntax element includes at least an index of optimal candidate motion information of a current block; determining, based on the syntax element, to construct a first list or a second list for the current block, where the first list is a block-based candidate motion information list, and the second list is a subblock-based candidate motion information list; determining optimal motion information from the first list or the second list based on the index; and predicting the current block based on the optimal motion information. In this method, the block-based candidate motion information list and the subblock-based candidate motion information list are distinguished from each other. This effectively reduces transmission costs of the optimal candidate motion information.

Abstract: In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.

Abstract: The present disclosure provides an auxiliary communication method and system, a device having base station function and a terminal. The auxiliary communication method includes: determining whether it is needed to provide auxiliary communication for any terminal according to channel quality of communication channels with the any terminal and data transmission requirement of the any terminal; selecting a specified terminal which is connected to the device having the base station function as an auxiliary terminal for assisting communication of the any terminal, when it is determined that it is needed to provide auxiliary communication for the any terminal; communicating with the any terminal through the auxiliary terminal. The present disclosure enables accurately to determine the terminal assisted in communication. Wasting communication sources and blind assistance are avoided. Higher channel quality of the terminal between the terminal and the base station and higher data transmission rate can be ensured.