Patents by Inventor Ting Han

Ting Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250046344
    Abstract: The present disclosure relates to a method, apparatus, device, storage medium and program product for processing multimedia data. The method comprises: acquiring first multimedia draft data, wherein the first multimedia draft data is generated based on a segmented recording operation, video materials collected by the segmented recording operation being used to form video track segments in the first multimedia draft data; importing the first multimedia draft data into a first editor, so that the video track segments are displayed on a video editing track of the first editor; updating the first multimedia draft data in response to triggering a video editing operation for the video track segments on the first editor, to obtain second multimedia draft data; and generating a target video based on the second multimedia draft data in response to a trigger operation of video synthesis.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Inventors: Zhanpeng HUANG, Guangde HUANG, Hengan WU, Rongtao YANG, Ting LUO, Yihan YANG, Xuyue HAN
  • Publication number: 20250027886
    Abstract: A defect inspection method, an inspection system, and a non-transitory computer-readable storage medium are provided. The defect inspection method includes providing a processed image and a reference image of a wafer, both the processed image and the reference image comprising a pattern of interest; determining the processed image as a qualified image in response to a matching ratio that reflects a percentage of correctly aligned features of the pattern of interest between the processed image and the reference image is above a first predetermined threshold; selecting a first feature of the qualified image; selecting a second feature of the reference image corresponding to the first feature of the processed image; comparing the qualified image with the reference image to determine a variation of the first feature with respect to the second feature; and detecting a defect of the wafer based on a comparison of the first and second features.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 23, 2025
    Inventors: SHAO-CHIEN CHIU, TING-HAN LIN, CHING-YI LIN, TO-YU CHEN
  • Patent number: 12177599
    Abstract: An image capturing method, applicable to an electronic device including an image capturing device and a processor, is provided. The image capturing device has a field of view (FOV). The image capturing method includes: capturing a plurality of images of the FOV by using the image capturing device, and recording a plurality of images within a capture frame in the FOV from the images, where a capturing range of the capture frame is smaller than or equal to the FOV; moving the capture frame to a perspective-moving target within the FOV in response to a setting operation on the perspective-moving target; and generating a moving-perspective video from the recorded images.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: December 24, 2024
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Ting-Han Chang, ChunYen Liao, Ching Xsuan Chen
  • Publication number: 20240414921
    Abstract: A memory device includes a substrate, a composite stacked structure, multiple first insulating structures, and multiple through vias. The substrate includes a memory plane region and a periphery region. The composite stacked structure is located on the substrate in the memory plane region and the periphery region, wherein the composite stacked structure includes a first stacked structure. The first stacked structure includes multiple first insulating layers and multiple intermediate layers alternately stacked on each other, and is located on the substrate in the periphery region. The first insulating structures are separated from each other, extend through the first stacked structure in the periphery region, and are respectively surrounded by the first insulating layers and the intermediate layers. The through vias extend through one of the first insulating structures.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 12, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Chen-Yu Cheng, Tzung-Ting Han
  • Patent number: 12157205
    Abstract: The present disclosure discloses a flamed-based vacuum generator, including a shell and a combustion assembly, where the shell has a cavity, the cavity being a space having at least one opening, and the combustion assembly includes a combustible object and an igniter, the igniter being configured to ignite the combustible object, the combustible object generating a flame in the cavity, and the flame extinguishing in the cavity. In the present disclosure, through in-depth study of the internal mechanism of vacuum generated by flame combustion, it is found that the extinguishing process of a flame is the key to the generation of vacuum, and a larger flame and more sufficient combustion indicate a higher vacuum pressure generated in the cavity after the flame is extinguished.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: December 3, 2024
    Assignee: ZHEJIANG UNIVERSITY
    Inventors: Xin Li, Xufeng Shen, Ting Han, Yingjie He
  • Publication number: 20240379066
    Abstract: A method for driving a display apparatus includes: in a first refresh period which corresponds to a first refresh rate and includes a first effective phase and first ineffective phase(s), outputting a first image frame signal to a display panel of the display apparatus in the first effective phase, and outputting a first ineffective data signal to the display panel in a first ineffective phase; and in a second refresh period which corresponds to a second refresh rate and includes a second effective phase and second ineffective phase(s), outputting a second image frame signal to the display panel in the second effective phase, and outputting a second ineffective data signal to the display panel in a second ineffective phase. The first refresh rate is different from the second refresh rate, and the first ineffective data signal and the second ineffective data signal have different magnitudes in voltage.
    Type: Application
    Filed: March 30, 2022
    Publication date: November 14, 2024
    Applicants: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuanzhang ZHU, Jian LI, Ting HAN, Guoqiang WU, Shuai HOU
  • Publication number: 20240365568
    Abstract: Methods, systems and apparatus for three-dimensional (3D) memory devices are provided. In one aspect, a semiconductor device includes: an array-side structure and a device-side structure. The array-side structure includes a memory array of memory cells and an array-side integrated circuit conductively coupled to the memory array. The device-side structure includes a device-side integrated circuit. The array-side structure and the device-side structure are integrated together with one or more connection pads therebetween. The array-side integrated circuit and the device-side integrated circuit are conductively coupled to each other through at least one of the one or more connection pads and configured to perform one or more operations on the memory array.
    Type: Application
    Filed: April 26, 2023
    Publication date: October 31, 2024
    Applicant: Macronix International Co., Ltd.
    Inventors: Chen-Yu Cheng, Tzung-Ting Han
  • Publication number: 20240355732
    Abstract: A memory device includes first and second interconnect structures, a stacked structure, a stop layer and channel pillar structures over a substrate. The stacked structure is located between the first and the second interconnection structures. The stop layer is located between the stacked structure and the second interconnect structure. Each channel pillar structure includes a channel pillar, a first channel plug and a second channel plug. The channel pillar extends through the stacked structure and the stop layer. The first channel plug is located at a first end of the channel pillar and connected to the first interconnection structure. The second channel plug is located at a second end of the channel pillar and connected to the second interconnection structure. A bottom surface of the second channel plug is closer to the substrate than a bottom surface of the stop layer.
    Type: Application
    Filed: April 19, 2023
    Publication date: October 24, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Chen-Yu Cheng, Chih-Kai Yang, Tzung-Ting Han
  • Publication number: 20240284669
    Abstract: A memory device includes a substrate and a stack structure. A lower portion of the stack structure includes a first global selection line structure and a second global selection line structure. The first global selection line structure includes a first long strip, a first short strip and a first connection part connecting the first long strip and the first short strip. The first long strip and the second strip extend in a first direction, and the first connection part extends in a second direction different from the first direction. The first long strip passes through a staircase structure area from a first memory array area extending continuously to a second memory array area. The second global selection line structure is adjacent to the first global selection line structure and is divided into two portions separated from each other by the first connection part of the first global selection line structure.
    Type: Application
    Filed: February 16, 2023
    Publication date: August 22, 2024
    Applicant: MACRONIX International Co. Ltd.
    Inventors: Chen-Yu Cheng, Tzung-Ting Han
  • Patent number: 12069861
    Abstract: Provided is a memory device including a stack structure, a first set of vertical channel structures, a second set of vertical channel structures and a first slit. The stack structure is disposed on a substrate, wherein a top surface of the substrate is parallel to a plane defined by a X direction and a Y direction perpendicular to the X direction. The first set of vertical channel structures and the second set of vertical channel structures are arranged along the Y direction and penetrating through the stack structure along a Z direction vertical to the plane to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure along the Z direction to expose the substrate, wherein the first slit includes a plurality of first sub-slits discretely disposed along the X direction.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: August 20, 2024
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chih-Kai Yang, Tzung-Ting Han
  • Patent number: 12062615
    Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: August 13, 2024
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ching Hung Wang, Shih Chin Lee, Chen-Yu Cheng, Tzung-Ting Han
  • Publication number: 20240247100
    Abstract: The present application is directed to a cleavable polymer comprising one or more repeat units containing monomer A and one or more repeat units containing monomer B, wherein repeat unit containing monomer A and repeat unit containing monomer B are as described herein and to a process of preparing such a cleavable polymer. The present application is also directed to a cleavable polymer comprising one or more repeat units containing monomer C and one or more repeat units containing monomer D, wherein repeat unit containing monomer C and repeat unit containing monomer D are as described herein.
    Type: Application
    Filed: December 27, 2023
    Publication date: July 25, 2024
    Inventors: Eric William Cochran, George A. Kraus, Michael J. Forrester, Aleksei Ananin, Ting-Han Lee, Aaron David Sadow, Nacu Hernandez, Dhananjay Dileep
  • Patent number: 12048154
    Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: July 23, 2024
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Hong-Ji Lee, Tzung-Ting Han, Lo Yueh Lin, Chih-Chin Chang, Yu-Fong Huang, Yu-Hsiang Yeh
  • Publication number: 20240224981
    Abstract: A cover body for weed removing tool includes a heat dissipation port for heat dissipation. A cover sheet for regulating a size of the heat dissipation port is arranged at a position on the cover body corresponding to the heat dissipation port, and the cover sheet is connected to the cover body, and is subject to displacement relative to the cover body.
    Type: Application
    Filed: January 22, 2024
    Publication date: July 11, 2024
    Applicant: Zhejiang Prulde Electric Appliance Co., Ltd.
    Inventors: Ting Han, Wei-Ming Yang
  • Patent number: 12015214
    Abstract: An antenna structure and an electronic device are provided. The antenna structure includes a substrate with opposing first and second surfaces, a first radiating element with a first radiating portion and a second radiating portion, a third radiating portion, a feeding portion, and a grounding portion that are connected to the first radiating portion, a second radiating element separate from but coupling with the first radiating portion, a grounding element connected to the grounding portion, and a feeding element. The first radiating portion, the feeding portion, and the grounding portion are disposed on the first surface. The second radiating portion and the third radiating portion are disposed on the second surface. A projected area of the second radiating portion onto the first surface partially overlaps with the feeding portion. A projected area of the third radiating portion onto the first surface partially overlaps with the grounding portion.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: June 18, 2024
    Assignee: WISTRON NEWEB CORPORATION
    Inventors: Chia-Hao Chang, Chung-Che Lien, Ting-Han Shih
  • Patent number: 12002401
    Abstract: A gamma correction method and apparatus, electronic device and readable storage medium.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: June 4, 2024
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Ting Han, Yuanzhang Zhu
  • Patent number: 11991479
    Abstract: The disclosure provides a time-lapse photographic device. The time-lapse photographic device includes a camera module, a drive module, an environment detection module, and a control unit. The drive module is connected to the camera module to drive the camera module to rotate. The environment detection module is configured to detect an external environment of the time-lapse photographic device to generate an environment detection signal. The control unit is electrically connected to the camera module, the drive module, and the environment detection module. The control unit generates, according to a shooting stop parameter, a plurality of intermittent drive signals to control the drive module, and controls the camera module to shoot at intervals of the drive signals. The control unit adjusts operation of at least one of the camera module and the drive module according to the environment detection signal.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: May 21, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Hsin-Yi Pu, Kai-Yu Hsu, Lai-Peng Wong, Chieh Li, Ting-Han Chang, Ching-Xsuan Chen
  • Publication number: 20240164099
    Abstract: An integrated circuit structure includes a substrate, semiconductor devices, an inter-layer dielectric (ILD) structure, an interconnect, a dielectric layer, an etching barrier layer, a conductive layer, and memory units. The semiconductor devices are on the substrate. The ILD structure is over the semiconductor devices. The interconnect is in the ILD structure and electrically connected to the semiconductor devices. The dielectric layer is over the ILD structure. The etching barrier layer is on the first dielectric layer. The conductive layer is on the etching barrier layer. The memory units are stacked in a vertical direction over the etching barrier layer.
    Type: Application
    Filed: March 15, 2023
    Publication date: May 16, 2024
    Inventors: Hong-Ji LEE, Tzung-Ting HAN, Chang-Wen JIAN
  • Publication number: 20240131086
    Abstract: The present disclosure provides use of Clostridium ghonii combined with a tumor angiogenesis inhibitor in preparing a pharmaceutical product for treating a tumor. The present disclosure further provides a drug for treating a tumor, where the drug includes active ingredients of Clostridium ghonii and a tumor angiogenesis inhibitor.
    Type: Application
    Filed: October 9, 2022
    Publication date: April 25, 2024
    Inventors: Yong Wang, Yuanyuan Liu, Wenhua Zhang, Yanqiu Xing, Shaopeng Wang, Dan Wang, Hong Zhu, Xinglu Xu, Shengbiao Jiang, Xiaonan Li, Jiahui Zheng, Rong Zhang, Dongxia Yang, Yuxia Gao, Shili Shao, Ting Han
  • Publication number: 20240115627
    Abstract: The present disclosure relates to use of a Clostridium ghonii spore combined with pembrolizumab in cancer treatment. It is found for the first time that the Clostridium ghonii spore combined with pembrolizumab can significantly improve a curative effect of colon cancer and reduce a dose of the pembrolizumab, and thus is efficient and low-toxic. Oncolysis by Clostridium ghonii can affect immunogenicity of a tumor microenvironment (TME) by various ways, converts an immunosuppressive state of the TME into an immune-activated state, adjusts the immunosuppressive TME, and breaks an immune tolerance. An optimal combination of the Clostridium ghonii spore and the pembrolizumab thoroughly removes about 20% of mouse tumor tissues. A benefit range of patients with tumors treated by a PD-1 antibody is expanded. The combination even has an obvious curative effect on patients failed the treatment by the PD-1 antibody.
    Type: Application
    Filed: October 9, 2022
    Publication date: April 11, 2024
    Inventors: Yong Wang, Hong Zhu, Wenhua Zhang, Yanqiu Xing, Dan Wang, Yuanyuan Liu, Shaopeng Wang, Jiahui Zheng, Rong Zhang, Xiaonan Li, Xinglu Xu, Shengbiao Jiang, Lichao Xing, Yuxia Gao, Shili Shao, Ting Han