Abstract: A method for driving a display apparatus includes: in a first refresh period which corresponds to a first refresh rate and includes a first effective phase and first ineffective phase(s), outputting a first image frame signal to a display panel of the display apparatus in the first effective phase, and outputting a first ineffective data signal to the display panel in a first ineffective phase; and in a second refresh period which corresponds to a second refresh rate and includes a second effective phase and second ineffective phase(s), outputting a second image frame signal to the display panel in the second effective phase, and outputting a second ineffective data signal to the display panel in a second ineffective phase. The first refresh rate is different from the second refresh rate, and the first ineffective data signal and the second ineffective data signal have different magnitudes in voltage.

Abstract: An electronic device and an antenna structure are provided. The electronic device includes a housing and an antenna structure which includes a first radiating element with a first radiating part, a feed part, and a grounding part, a second radiating element with five branches, a grounding element connected to the grounding part, a feed element connected to the feed part, a switching circuit electrically connected to the third branch, and a proximity sensing circuit electrically connected to the fourth branch. The first branch and the second branch intersect at a first branching point, the third branch and the fourth branch intersect at a second branching point. The fifth branch is connected between the first branching point and the second branching point. The first radiating part extends between the first branch and the second branch so the first radiating part and the second radiating element couple with each other.

Abstract: An electronic device includes a housing and an antenna module. The antenna module is disposed in the housing. The antenna module includes a first radiating element, a switching circuit, a proximity sensing circuit, a second radiating element, and a third radiating element. The first radiating element includes a feeding portion, a radiating portion, and a grounding portion. The feeding portion and the grounding portion are connected to the radiating portion. The second radiating element is electrically connected to the switching circuit. The second radiating element and the radiating portion are separated from and coupled with each other. The third radiating element is electrically connected to the proximity sensing circuit. The third radiating element and the second radiating element are separated from each other, and the third radiating element and the radiating portion are separated from and coupled with each other.

Abstract: A computer-implemented method for supporting execution of batch production by a production system includes, over a sequence of steps: acquiring a system state defined by a shop floor status, inventory status and a demand of the product types, and processing the system state using a reinforcement learned policy including a deep learning model to output a control action defining an integer batch size of a selected product type. The control action is determined by using learned parameters of the deep learning model to compute logits for a categorical distribution of predicted product types and a categorical distribution of predicted batch sizes from the system state. The logits are processed to transform the categorical distribution of predicted product types into an encoding of the selected product type and reduce the categorical distribution of predicted batch sizes into an integer batch size, for producing a next batch on the shop floor.

Abstract: An electric vehicle fleet operations system includes electric vehicle charging stations; electric energy storage batteries; solar panels; a fleet of electric vehicles adapted to charge using the electric vehicle charging stations; a forecasting module predicting operational parameters including electricity prices, weather variables, power production of the solar panels, and emission factors of the electrical power distribution grid; a surrogate module predicting, based on the operational parameters, energy consumption of the fleet of electric vehicles; an optimization module adapted to compute, based on the operational parameters and the energy consumption, optimal operational tasks for the fleet of electric vehicles and for the electric energy storage batteries; and a communications subsystem adapted to communicate the operational tasks to the fleet of electric vehicles and to the electric energy storage batteries.

Abstract: An antenna structure is disposed on a heat sink. The heat sink includes a plurality of cooling fins. The antenna structure includes a feeding source, a connecting member connected to the feeding source, and an antenna unit. The feeding source is located between two of the adjacent cooling fins. The antenna unit includes a radiation portion connected to the connecting member, a first segment, a second segment, and a third segment. The first segment and the second segment are connected to the radiation portion. The second segment is arranged in alignment with the first segment and a distance apart from the cooling fins. The third segment is connected to the feeding source and overlaps with at least one of the cooling fins.

Abstract: Provided is a semiconductor device for manufacturing a 3D NAND flash memory with high capacity and high performance. The semiconductor device includes: a first device structure layer on a substrate; an interconnect structure layer on the first device structure layer, which includes first pads at a surface thereof; a second device structure layer on the interconnect structure layer, which includes second pads at a surface thereof; a pattern structure at an interface between the interconnect structure layer and the second device structure layer; a first seal ring at the surface of the interconnect structure layer, which surrounds the pattern structure; a second seal ring at the surface of the second device structure layer, which surrounds the pattern structure. The first pad is connected to the second pad, and the first seal ring is connected to the second seal ring.

Abstract: A memory device includes a stack structure, a first stop layer, a dielectric layer, at least one separation wall and a conductive plug. The stacked structure is located over a substrate. The stacked structure has an opening exposing a stepped structure of the stacked structure. The first stop layer covers the stepped structure and at least at least one portion of sidewalls of the opening. The dielectric layer fills the opening and covers the first stop layer. The separation wall extends through the dielectric layer and the first stop layer in the opening. The conductive plug extends through the dielectric layer and the first stop layer, and is electrically connected to the stepped structure. The memory device may be a 3D NAND flash memory with high capacity and high performance.

Abstract: A semiconductor device includes a circuit board, a bottom plate, landing pads, a stack, support pillars, and memory pillars. The circuit board includes circuit structures and wires and has a peripheral area, an array area and a staircase area disposed between the peripheral area and the array area. The bottom plate is disposed on the circuit board, and the bottom plate includes a bottom conductive layer. The landing pads are embedded in at least a top portion of the bottom conductive layer and contact the bottom conductive layer in the staircase area. The stack is disposed on the bottom plate, and includes conductive layers and insulating layers alternately stacked along a first direction. The support pillars pass through the stack along the first direction and extend to the landing pads in the staircase area. The memory pillars pass through the stack along the first direction in the array area.

Abstract: A defect inspection method, an inspection system, and a non-transitory computer-readable storage medium are provided. The defect inspection method includes providing a processed image and a reference image of a wafer, both the processed image and the reference image comprising a pattern of interest; determining the processed image as a qualified image in response to a matching ratio that reflects a percentage of correctly aligned features of the pattern of interest between the processed image and the reference image is above a first predetermined threshold; selecting a first feature of the qualified image; selecting a second feature of the reference image corresponding to the first feature of the processed image; comparing the qualified image with the reference image to determine a variation of the first feature with respect to the second feature; and detecting a defect of the wafer based on a comparison of the first and second features.

Abstract: An image capturing method, applicable to an electronic device including an image capturing device and a processor, is provided. The image capturing device has a field of view (FOV). The image capturing method includes: capturing a plurality of images of the FOV by using the image capturing device, and recording a plurality of images within a capture frame in the FOV from the images, where a capturing range of the capture frame is smaller than or equal to the FOV; moving the capture frame to a perspective-moving target within the FOV in response to a setting operation on the perspective-moving target; and generating a moving-perspective video from the recorded images.

Abstract: A memory device includes a substrate, a composite stacked structure, multiple first insulating structures, and multiple through vias. The substrate includes a memory plane region and a periphery region. The composite stacked structure is located on the substrate in the memory plane region and the periphery region, wherein the composite stacked structure includes a first stacked structure. The first stacked structure includes multiple first insulating layers and multiple intermediate layers alternately stacked on each other, and is located on the substrate in the periphery region. The first insulating structures are separated from each other, extend through the first stacked structure in the periphery region, and are respectively surrounded by the first insulating layers and the intermediate layers. The through vias extend through one of the first insulating structures.

Abstract: The present disclosure discloses a flamed-based vacuum generator, including a shell and a combustion assembly, where the shell has a cavity, the cavity being a space having at least one opening, and the combustion assembly includes a combustible object and an igniter, the igniter being configured to ignite the combustible object, the combustible object generating a flame in the cavity, and the flame extinguishing in the cavity. In the present disclosure, through in-depth study of the internal mechanism of vacuum generated by flame combustion, it is found that the extinguishing process of a flame is the key to the generation of vacuum, and a larger flame and more sufficient combustion indicate a higher vacuum pressure generated in the cavity after the flame is extinguished.

Abstract: A method for driving a display apparatus includes: in a first refresh period which corresponds to a first refresh rate and includes a first effective phase and first ineffective phase(s), outputting a first image frame signal to a display panel of the display apparatus in the first effective phase, and outputting a first ineffective data signal to the display panel in a first ineffective phase; and in a second refresh period which corresponds to a second refresh rate and includes a second effective phase and second ineffective phase(s), outputting a second image frame signal to the display panel in the second effective phase, and outputting a second ineffective data signal to the display panel in a second ineffective phase. The first refresh rate is different from the second refresh rate, and the first ineffective data signal and the second ineffective data signal have different magnitudes in voltage.

Abstract: Methods, systems and apparatus for three-dimensional (3D) memory devices are provided. In one aspect, a semiconductor device includes: an array-side structure and a device-side structure. The array-side structure includes a memory array of memory cells and an array-side integrated circuit conductively coupled to the memory array. The device-side structure includes a device-side integrated circuit. The array-side structure and the device-side structure are integrated together with one or more connection pads therebetween. The array-side integrated circuit and the device-side integrated circuit are conductively coupled to each other through at least one of the one or more connection pads and configured to perform one or more operations on the memory array.

Abstract: A memory device includes first and second interconnect structures, a stacked structure, a stop layer and channel pillar structures over a substrate. The stacked structure is located between the first and the second interconnection structures. The stop layer is located between the stacked structure and the second interconnect structure. Each channel pillar structure includes a channel pillar, a first channel plug and a second channel plug. The channel pillar extends through the stacked structure and the stop layer. The first channel plug is located at a first end of the channel pillar and connected to the first interconnection structure. The second channel plug is located at a second end of the channel pillar and connected to the second interconnection structure. A bottom surface of the second channel plug is closer to the substrate than a bottom surface of the stop layer.

Abstract: A memory device includes a substrate and a stack structure. A lower portion of the stack structure includes a first global selection line structure and a second global selection line structure. The first global selection line structure includes a first long strip, a first short strip and a first connection part connecting the first long strip and the first short strip. The first long strip and the second strip extend in a first direction, and the first connection part extends in a second direction different from the first direction. The first long strip passes through a staircase structure area from a first memory array area extending continuously to a second memory array area. The second global selection line structure is adjacent to the first global selection line structure and is divided into two portions separated from each other by the first connection part of the first global selection line structure.

Abstract: Provided is a memory device including a stack structure, a first set of vertical channel structures, a second set of vertical channel structures and a first slit. The stack structure is disposed on a substrate, wherein a top surface of the substrate is parallel to a plane defined by a X direction and a Y direction perpendicular to the X direction. The first set of vertical channel structures and the second set of vertical channel structures are arranged along the Y direction and penetrating through the stack structure along a Z direction vertical to the plane to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure along the Z direction to expose the substrate, wherein the first slit includes a plurality of first sub-slits discretely disposed along the X direction.

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.

Abstract: The present application is directed to a cleavable polymer comprising one or more repeat units containing monomer A and one or more repeat units containing monomer B, wherein repeat unit containing monomer A and repeat unit containing monomer B are as described herein and to a process of preparing such a cleavable polymer. The present application is also directed to a cleavable polymer comprising one or more repeat units containing monomer C and one or more repeat units containing monomer D, wherein repeat unit containing monomer C and repeat unit containing monomer D are as described herein.