Abstract: A complementary field-effect transistor (CFET) device includes: a fin; first channel regions disposed vertically over the fin; second channel regions disposed vertically over the first channel regions; an isolation structure between the first and the second channel regions; a first etch stop layer (ESL) on a lower surface of the isolation structure; a second ESL on an upper surface of the isolation structure, where the first ESL, the second ESL, the first channel regions, and the second channel regions are a same semiconductor material; first source/drain regions at opposing ends of the first channel regions; second source/drain regions at opposing ends of the second channel regions; dielectric structures at opposing ends of the isolation structure and disposed vertically between the first and the second source/drain regions; a first gate structure around the first channel regions; and a second gate structure around the second channel regions.

Abstract: Methods, apparatus, and systems that relate to UE information reporting and packet delay management technique in communication systems. In one example aspect, a method for digital communication includes transmitting, by a wireless device, a signal including a buffer size reporting information to a first communication device, wherein the buffer size reporting information comprises an identity information, a buffer size information, and a time information.

Abstract: A semiconductor device includes a substrate, a plurality of memory arrays and a plurality of capacitors. The substrate includes a plurality of memory array regions. Each memory array region includes a plurality of memory blocks and a plurality of dummy blocks. The dummy blocks are located along a boundary of the memory blocks. The plurality of memory arrays are disposed in the plurality of memory blocks. The plurality of capacitors are disposed in the plurality of dummy blocks along the boundary of the plurality of memory blocks. The plurality of memory arrays may include 3D NAND flash memories with high capacity and high performance.

Abstract: A memory device includes: an interconnect structure, a staircase structure, a dielectric layer and a stop structure. The interconnect structure is located above a substrate. The staircase structure is located above the interconnect structure. The dielectric layer is located above the interconnect structure and covers the staircase structure. The stop structure is located between the interconnect structure and the staircase structure, and between the interconnect structure and the dielectric layer, and the stop structure has an opening exposing the interconnect structure. The first contact extends through the dielectric layer and the opening, and is connected to the interconnect of the interconnect structure. The middle width of the opening is not equal to the top width of the opening, or the middle width of the opening is not equal to the bottom width of the opening. The memory device may be 3D NAND flash memory with high capacity and high performance.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: Disclosed are a receiver control circuit and a terminal. The receiver control circuit includes: a smart power amplifier module, a coder-decoder, and a receiver. The smart power amplifier module is electrically connected to the receiver by a first switch module. The first switch module includes a first switch component unit that is formed by a metal oxide semiconductor field-effect transistor (MOSFET). The first switch module further includes a first follower unit, where the first follower unit is configured to keep an unchanged voltage difference between a gate electrode of the MOSFET of the first switch component unit and a drain electrode thereof, and a gate electrode voltage of the MOSFET of the first switch component unit is greater than a drain electrode voltage thereof. The coder-decoder is electrically connected to the receiver by the second switch module. The second switch module includes a second switch component unit.

Abstract: The present disclosure relates to a modified antibody, or antigen-binding fragment thereof, specific for nectin cell adhesion molecule 4 (nectin-4). The present disclosure also relates to a method of detecting or diagnosing whether a subject has, or is at risk of developing a tumor, or assessing a prognosis of a tumor and a pharmaceutical composition for use in treating, prophylactic treating and/or preventing tumor in a subject afflicted with the tumor.

Abstract: A power module having a bottom substrate, a device substrate arranged on the bottom substrate and an inductor assembly arranged on the device substrate. The inductor assembly has a first winding, a second winding, a first magnetic core part and a second magnetic core part. The first magnetic core part has a first portion disposed on a first horizontal level and a second portion disposed on a second horizontal level. The second magnetic core part has a first portion disposed on the second horizontal level and a second portion disposed on the first horizontal level. The first and second magnetic core parts are assembled to accommodate the first winding between the first portions of the first and second magnetic core part, and to accommodate the second winding between the second portions of the first and second magnetic core part.

Abstract: A method and apparatus for determining the orientation of a subject during medical imaging, and a medical imaging system is provided. The method includes: acquiring an image sequence of a subject captured by a camera, the image sequence comprising a plurality of images based on a time sequence; determining, based on the image sequence, whether the state of the subject is abnormal; and in response to a determination result that the state of the subject is abnormal, determining the orientation of the subject by using a first orientation or a second orientation, wherein the first orientation is the orientation of the subject determined based on an image before a period when the state of the subject is determined to be abnormal, and the second orientation is the orientation of the subject determined based on an image after the period when the state of the subject is determined to be abnormal.

Abstract: Embodiments of the present disclosure provide a method and apparatus for video processing, a device, and a medium, the method includes: distributing first shoot frames to a recording unit and a content analysis unit during a shooting process; performing a recording processing on the first shoot frames by the recording unit to obtain a recorded video; and performing a content analysis processing on the first shoot frames by the content analysis unit to obtain content analysis results of the first shoot frames; in case of obtaining the recorded video, determining a content analysis result of the recorded video based on the content analysis results of the first shoot frames; the content analysis result of the recorded video is used when performing an edit processing on the recorded video.

Abstract: A power module, having a bottom substrate, a device substrate arranged on the bottom substrate and an inductor assembly arranged on the device substrate. The device substrate having a first power device chip and a second power device chip embedded within the device substrate. Each power device chip has a first surface and a second surface. The first surface of each power device chip is covered by a top heat layer, and the second surface of each power device chip has a plurality of pins or pads exposed on the second surface of the device substrate, and connected to the bottom substrate.

Abstract: A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.

Abstract: A power module has an inductor assembly and a device substrate. The inductor assembly comprises a magnetic core, a first winding and a second winding. Each of the first winding and the second winding has a first end and a second end exposed at the second surface of the inductor assembly. The device substrate has a first power device chip and a second power device chip at least partially embedded within the device substrate. The device substrate further has a first top heat layer at least partially covering the first power device chip and a second top heat layer at least partially covering the second power device chip. The first end of the first winding is electrically connected to the first top heat layer, and the first end of the second winding is electrically connected to the second top heat layer.

Abstract: A semiconductor device includes a first fin-shaped structure and a second fin-shaped structure on a substrate, a bump between the first fin-shaped structure and the second fin-shaped structure, a first recess between the first fin-shaped structure and the bump, and a second recess between the second fin-shaped structure and the bump. Preferably, a top surface of the bump includes a curve concave upward, a width of the bump is greater than twice the width of the first fin-shaped structure, and a height of the bump is less than one fourth of the height of the first fin-shaped structure.

Abstract: EUV masks and methods of fabrication thereof are described herein. An exemplary method includes receiving an EUV mask having a multilayer structure, a capping layer disposed over the multilayer structure, a patterned absorber layer disposed over the capping layer, and a patterned hard mask disposed over the patterned absorber layer. The method further includes removing the patterned hard mask by performing a first etching process to partially remove the patterned hard mask and performing a second etching process to remove a remainder of the patterned hard mask. The first etching process uses a first etchant, and the second etching process uses a second etchant. The second etchant is different than the first etchant. In some embodiments, the first etchant is a halogen-based plasma (e.g., a Cl2 plasma), and the second etchant is a halogen-and-oxygen-based plasma (e.g., a Cl2+O2 plasma).

Abstract: A method for filling a gap includes: filling a dielectric layer in the gap so that a seam is formed in the dielectric layer, the dielectric layer including two surface portions at two opposite sides of the seam, respectively; introducing a surface modification agent into the seam such that each of the two surface portions has first functional groups and second functional groups; forming a stress layer on the dielectric layer to cover the seam, the stress layer including a material different from that of the dielectric layer; and applying an energy field to permit the two surface portions to bond with each other through reaction between the first functional groups and the second functional groups.

Abstract: The present application discloses a crosstalk elimination method and a playback system for crosstalk elimination. The method includes steps: inputting a first test signal into a signal processor via an audio source input cable; detecting a first crosstalk signal generated by a second speaker and caused by a first test signal when the signal processor transmitting the first test signal to the first speaker; reversing the detected first crosstalk signal to a first reversed signal having equal volume and opposite phase, wherein when the signal processor transmits the first test signal to the first speaker again, the second speaker receives the first crosstalk signal and emits a first crosstalk sound, the first reversed signal is transmitted to the second speaker to emit a first reversed phase sound, and the first reversed phase sound eliminates the first crosstalk sound.

Abstract: A method includes forming a metal layer over a dielectric layer; forming hard masks over the metal layer; etching the metal layer using the hard masks as etch mask to form metal features; selectively forming dielectric liners on opposite sidewalls of each of the metal features, while leaving surfaces of the hard masks and the dielectric layer exposed by the dielectric liners; and forming an inter-metal dielectric layer laterally surrounding the metal features.

Abstract: The anti-twist structure includes a base, a lens housing, an elastic sheet and a yoke member. The lens housing has a margin wall with a first protrusion, a second protrusion and a contact portion. The contact portion is extended outwardly the first protrusion, and the second protrusion is protruded from the contact portion. The first protrusion and the second protrusion are protruded along an axial direction substantially perpendicular to the margin wall. The elastic sheet is disposed on the contact portion. When the lens housing deflects from the horizontal reference line to a maximum value of the deflectable angle, the first protrusion abuts against an upper wall of the yoke member, the second protrusion abuts against the elastic sheet, and the contact portion abuts against the elastic sheet or the upper wall at the same time, whereby the lens housing and the yoke member interfere with each other.